公开(公告)号：US20080181048A1

公开(公告)日：2008-07-31

申请号：US12007855

申请日：2008-01-16

Applicant: Yong-Joo Han

Inventor： Yong-Joo Han

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C16/349

Abstract: A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input address has been accessed the predetermined number of times or more.

Abstract translation: 存储单元访问方法可以包括接收输入地址，确定输入地址是否已被访问至少预定次数，以及当确定输入地址被访问时转换由输入地址启用的存储单元 预定次数以上。

公开(公告)号：US20080285346A1

公开(公告)日：2008-11-20

申请号：US12219600

申请日：2008-07-24

Applicant: Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

Inventor： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

IPC: G11C16/04 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

Abstract translation: 解码器，存储器系统及其物理位置转换方法可以检测输入地址的地址计数是否等于或大于预定值。 如果地址计数等于或大于预定值，则可以转换对应于输入地址的半导体存储器件的物理位置。

公开(公告)号：US07929372B2

公开(公告)日：2011-04-19

申请号：US12219600

申请日：2008-07-24

Applicant: Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Choi Choe

Inventor： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Choi Choe

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

Abstract translation: 解码器，存储器系统及其物理位置转换方法可以检测输入地址的地址计数是否等于或大于预定值。 如果地址计数等于或大于预定值，则可以转换对应于输入地址的半导体存储器件的物理位置。

公开(公告)号：US07830742B2

公开(公告)日：2010-11-09

申请号：US12007855

申请日：2008-01-16

Applicant: Yong-Joo Han

Inventor： Yong-Joo Han

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C16/349

Abstract: A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input address has been accessed the predetermined number of times or more.

Abstract translation: 存储单元访问方法可以包括接收输入地址，确定输入地址是否已被访问至少预定次数，以及当确定输入地址被访问时转换由输入地址启用的存储单元 预定次数以上。

公开(公告)号：US5535152A

公开(公告)日：1996-07-09

申请号：US291943

申请日：1994-08-17

Applicant: Yong-Joo Han ,  Myung-Ho Bae

Inventor： Yong-Joo Han ,  Myung-Ho Bae

IPC: H01L27/04 ,  H01L27/02 ,  H01L27/10

CPC classification number: H01L27/0218

Abstract: A power supply arrangement for a semiconductor chip includes, in a first preferred embodiment, a power supply voltage line, a ground voltage line, an intermediate voltage line, a plurality of first noise reduction capacitors connected between the intermediate voltage line and the power supply voltage line, and a plurality of second noise reduction capacitors connected between the intermediate voltage line and the ground voltage line. In a second preferred embodiment, the power supply arrangement includes a power supply voltage line, a ground voltage line, a quiet power supply voltage line, a quiet ground voltage line, a plurality of first noise reduction capacitors connected between the power supply voltage line and the quiet ground voltage line, and a plurality of second noise reduction capacitors connected between the ground voltage line and the quiet power supply voltage line.

Abstract translation: 在第一优选实施例中，用于半导体芯片的电源装置包括电源电压线，接地电压线，中间电压线，连接在中间电压线和电源电压之间的多个第一降噪电容器 并且连接在中间电压线和地电压线之间的多个第二降噪电容器。 在第二优选实施例中，电源装置包括电源电压线，接地电压线，静态电源电压线，静态接地电压线，连接在电源电压线和电源电压线之间的多个第一降噪电容器 连接在地电压线和安静电源电压线之间的多个第二降噪电容器。