公开(公告)号：US20080285346A1

公开(公告)日：2008-11-20

申请号：US12219600

申请日：2008-07-24

申请人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

发明人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Chol Choe

IPC分类号： G11C16/04 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

摘要翻译： 解码器，存储器系统及其物理位置转换方法可以检测输入地址的地址计数是否等于或大于预定值。 如果地址计数等于或大于预定值，则可以转换对应于输入地址的半导体存储器件的物理位置。

公开(公告)号：US07929372B2

公开(公告)日：2011-04-19

申请号：US12219600

申请日：2008-07-24

申请人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Choi Choe

发明人： Yong-Joo Han ,  Dong-Jin Lee ,  Kwang-Choi Choe

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

摘要翻译： 解码器，存储器系统及其物理位置转换方法可以检测输入地址的地址计数是否等于或大于预定值。 如果地址计数等于或大于预定值，则可以转换对应于输入地址的半导体存储器件的物理位置。

公开(公告)号：US08120398B2

公开(公告)日：2012-02-21

申请号：US12911412

申请日：2010-10-25

申请人： Dong-Jin Lee

发明人： Dong-Jin Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0818 ,  H03L7/10

摘要： A delay locked loop (DLL) circuit has a first delay line that delays a received external clock signal for a fine delay time and then outputs a first internal clock signal; a duty cycle correction unit that corrects a duty cycle of the first internal clock signal and then outputs a second clock signal; a second delay line that delays the second clock signal for a coarse delay time and then outputs a second internal clock signal; and a phase detection and control unit that detects the difference between the phases of the external clock signal and the fed back second internal clock signal, and controls the fine delay time and the coarse delay time. The DLL circuit performs coarse locking and fine locking by using different type delay cells, and thus consumes a small amount of power and robustly withstands jitter and variation in PVT variables.

摘要翻译： 延迟锁定环（DLL）电路具有延迟接收到的外部时钟信号以获得精细延迟时间的第一延迟线，然后输出第一内部时钟信号; 占空比校正单元，校正第一内部时钟信号的占空比，然后输出第二时钟信号; 第二延迟线，延迟所述第二时钟信号的粗略延迟时间，然后输出第二内部时钟信号; 以及相位检测和控制单元，其检测外部时钟信号和反馈的第二内部时钟信号的相位之间的差异，并且控制精细延迟时间和粗略延迟时间。 DLL电路通过使用不同类型的延迟单元执行粗略锁定和精细锁定，从而消耗少量的功率，并且坚固地承受PVT变量的抖动和变化。

公开(公告)号：US08014643B2

公开(公告)日：2011-09-06

申请号：US12391075

申请日：2009-02-23

申请人： Beom-Hoan O ,  Dong-Jin Lee

发明人： Beom-Hoan O ,  Dong-Jin Lee

IPC分类号： G02B6/26

CPC分类号： G02B6/1225 ,  B82Y20/00

摘要： Disclosed herein is a photonic crystal waveguide inlet structure for improving coupling efficiency of a strip waveguide and a photonic crystal waveguide. The photonic crystal waveguide inlet structure includes an inlet region of the photonic crystal waveguide. The photonic crystal waveguide includes photonic crystals in which air holes are arranged in a triangle lattice shape in a dielectric, and a hybrid waveguide in which at least one of the air holes is removed, the hybrid waveguide spacing the inlet region apart from the strip waveguide.

摘要翻译： 本文公开了一种用于提高条形波导和光子晶体波导的耦合效率的光子晶体波导入口结构。 光子晶体波导入口结构包括光子晶体波导的入口区域。 光子晶体波导包括其中空气孔在电介质中以三角形格子形状布置的光子晶体和其中至少一个空气孔被去除的混合波导，该混合波导将入口区域与带状波导分开 。

公开(公告)号：US07560968B2

公开(公告)日：2009-07-14

申请号：US11609660

申请日：2006-12-12

申请人： Dong-Jin Lee

发明人： Dong-Jin Lee

IPC分类号： H03H11/26

CPC分类号： H03K17/0822 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4093 ,  G11C29/025 ,  G11C29/12 ,  G11C29/1201 ,  H03K17/6872 ,  H03K19/018528

摘要： An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The driving unit control unit includes a driving unit copying unit having the same construction as the driving unit and compares an output copying signal generated from the first and second driving signals by the driving unit copying unit with a reference voltage and generates the control signal that controls delays of the first and second driving signals in a test mode.

摘要翻译： 能够控制短路电流的输出驱动器包括驱动单元和驱动控制单元。 驱动单元响应于控制信号接收第一驱动信号和第二驱动信号，并产生输出信号。 驱动单元控制单元包括具有与驱动单元相同结构的驱动单元复制单元，并将由驱动单元复制单元产生的第一和第二驱动信号的输出复制信号与参考电压进行比较，并产生控制信号 在测试模式下第一和第二驱动信号的延迟。

公开(公告)号：US07440340B2

公开(公告)日：2008-10-21

申请号：US11252535

申请日：2005-10-18

申请人： Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

发明人： Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

IPC分类号： G11C5/14

CPC分类号： G11C7/1051 ,  G11C5/147 ,  G11C7/1048 ,  G11C7/1057

摘要： A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a first power supply voltage and pulls down the output terminal to a second power supply voltage based on an output data signal. The pull-down driver pre-emphasizes an initial stage of a pull-down driving operation of the output terminal based on the output data.

摘要翻译： 数据输出缓冲器包括输出端子，缓冲器和下拉驱动器。 输出端耦合到传输线的第一端，传输线在第二端耦合到上拉终端电阻。 缓冲器将输出端上拉至第一电源电压，并根据输出数据信号将输出端拉低至第二电源电压。 下拉驱动器基于输出数据预先强调输出端子的下拉驱动操作的初始阶段。

公开(公告)号：US20110148641A1

公开(公告)日：2011-06-23

申请号：US12972924

申请日：2010-12-20

申请人： Woo-Sug Jung ,  Jong-Arm Jun ,  Jong-Suk Chae ,  Dong-Jin Lee

发明人： Woo-Sug Jung ,  Jong-Arm Jun ,  Jong-Suk Chae ,  Dong-Jin Lee

IPC分类号： G08B23/00

CPC分类号： A61B5/11 ,  A61B5/0002 ,  A61B5/1101 ,  A61B5/1112 ,  A61B5/1118

摘要： Disclosed herein are an apparatus and method for detecting the survival status of a living thing. The apparatus for detecting the survival status of a living thing includes a tilt sensor, a determination unit, and a communication unit. The tilt sensor is attached to a target living thing, and detects minute vibrations generated by the motion of the target living thing. The determination unit determines the survival status of the target living thing for a preset update period based on the minute vibrations. The communication unit sends an update packet including determination results of the determination unit to an outside.

摘要翻译： 这里公开了一种用于检测生物体的生存状态的装置和方法。 用于检测生物的生存状态的装置包括倾斜传感器，确定单元和通信单元。 倾斜传感器附接到目标生物，并且检测由目标生物的运动产生的微小振动。 确定单元基于微小振动来确定目标生物在预设更新周期中的生存状态。 通信单元向外部发送包括确定单元的确定结果的更新分组。

公开(公告)号：US07894260B2

公开(公告)日：2011-02-22

申请号：US12195516

申请日：2008-08-21

申请人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

发明人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/105

摘要： A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

摘要翻译： 具有片上终端（ODT）电路和ODT方法的同步半导体存储器件通过执行与外部同步的ODT操作，满足ODT DC和AC参数规格并通过外部或内部控制执行自适应阻抗匹配 时钟。 具有用于与外部时钟同步地进行数据输出操作的数据输出电路的同步半导体存储器件包括ODT电路，用于产生具有与用于数据输出操作的数据输出上下信号相同的定时的ODT上下信号， 执行ODT操作。

公开(公告)号：US07426145B2

公开(公告)日：2008-09-16

申请号：US11802443

申请日：2007-05-23

申请人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

发明人： Dong-Jin Lee ,  Kye-Hyun Kyung ,  Chang-Sik Yoo

IPC分类号： G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/105

摘要： A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

摘要翻译： 具有片上终端（ODT）电路和ODT方法的同步半导体存储器件通过执行与外部同步的ODT操作，满足ODT DC和AC参数规格并通过外部或内部控制执行自适应阻抗匹配 时钟。 具有用于与外部时钟同步地进行数据输出操作的数据输出电路的同步半导体存储器件包括ODT电路，用于产生具有与用于数据输出操作的数据输出上下信号相同的定时的ODT上下信号， 执行ODT操作。

公开(公告)号：US20060152467A1

公开(公告)日：2006-07-13

申请号：US11327688

申请日：2006-01-06

申请人： Dong-Jin Lee

发明人： Dong-Jin Lee

IPC分类号： G09G3/36

CPC分类号： H03K19/0005 ,  G11C7/1051 ,  G11C7/1057 ,  H03K17/164

摘要： A data output driver and a semiconductor memory device having the same are disclosed. This data output driver includes: a rising transition slope adjuster including a plurality of first delay units cascade-connected to each other and receiving data and generating delayed data, each of the first delay units having a delay time which varies in response to a first control signal; a falling transition slope adjuster including a plurality of second delay units cascade-connected to each other and receiving inverted data and generating delayed inverted data, each of the second delay units having a delay time which varies in response to a second control signal; a pull-up driver including a plurality of pull-up circuits, the driving capabilities of the pull-up circuits being adjustable in response to a third control signal, each pull-up circuit pulling-up output data in response to each of the data and the delayed data; and a pull-down driver including a plurality of pull-down circuits, the driving capabilities of the pull-down circuits being adjustable in response to a fourth control signal, each pull-down circuit pulling-down output data in response to each of the inverted data and the delayed inverted data, wherein the first control signal varies in response to the third control signal, and wherein the second control signal varies in response to the fourth control signal. Accordingly, the rising and falling transition slopes of the output data can be constant even when the driving capability is varied, so that output data having desired characteristics can be produced.

摘要翻译： 公开了一种数据输出驱动器及其半导体存储器件。 该数据输出驱动器包括：上升过渡斜率调整器，包括彼此级联的多个第一延迟单元，并接收数据并产生延迟数据，每个第一延迟单元具有响应于第一控制而变化的延迟时间 信号; 一个下降的转变斜率调节器，包括彼此级联的多个第二延迟单元，并接收反相数据并产生延迟的反相数据，每个第二延迟单元具有响应于第二控制信号变化的延迟时间; 包括多个上拉电路的上拉驱动器，上拉电路的驱动能力可响应于第三控制信号而被调节，每个上拉电路响应于每个数据提取输出数据 和延迟数据; 以及包括多个下拉电路的下拉驱动器，所述下拉电路的驱动能力响应于第四控制信号而是可调节的，每个下拉电路根据每个下拉电路的每个下拉输出数据 反转数据和延迟反转数据，其中第一控制信号响应于第三控制信号而变化，并且其中第二控制信号响应于第四控制信号而变化。 因此，即使驱动能力变化，输出数据的上升和下降转换斜率也可以是恒定的，从而可以产生具有期望特性的输出数据。