Technique for switching between 1x and 2x oversampling rate in a TD-SCDMA receiver
    1.
    发明授权
    Technique for switching between 1x and 2x oversampling rate in a TD-SCDMA receiver 有权
    在TD-SCDMA接收机中切换1x和2x过采样率的技术

    公开(公告)号:US08548005B2

    公开(公告)日:2013-10-01

    申请号:US13090223

    申请日:2011-04-19

    IPC分类号: H04J13/00

    CPC分类号: H04B1/7105

    摘要: A TD-SCDMA receiver is provided that includes a joint detection (JD) block receiving a first input signal from a channel estimation block for signal detection. A short channel detection (SCD) block receives the first input signal and detecting the presence/absence of an AGWN-like channel based on the first input signal from the channel estimation block. The SCD block switches the JD block between 1× and 2× oversampling rates by sending to the JD block a second input signal.

    摘要翻译: 提供一种TD-SCDMA接收机,其包括从用于信号检测的信道估计块接收第一输入信号的联合检测(JD)块。 短信道检测(SCD)块基于来自信道估计块的第一输入信号接收第一输入信号并检测AGWN样信道的存在/不存在。 SCD块通过向JD块发送第二个输入信号来将JD块切换到1×和2×过采样率之间。

    TECHNIQUE FOR SWITCHING BETWEEN 1X AND 2X OVERSAMPLING RATE IN A TD-SCDMA RECEIVER
    2.
    发明申请
    TECHNIQUE FOR SWITCHING BETWEEN 1X AND 2X OVERSAMPLING RATE IN A TD-SCDMA RECEIVER 有权
    在TD-SCDMA接收机中切换1X和2X超频率的技术

    公开(公告)号:US20120269202A1

    公开(公告)日:2012-10-25

    申请号:US13090223

    申请日:2011-04-19

    IPC分类号: H04J13/00

    CPC分类号: H04B1/7105

    摘要: A TD-SCDMA receiver is provided that includes a joint detection (JD) block receiving a first input signal from a channel estimation block for signal detection. A short channel detection (SCD) block receives the first input signal and detecting the presence/absence of an AGWN-like channel based on the first input signal from the channel estimation block. The SCD block switches the JD block between 1× and 2× oversampling rates by sending to the JD block a second input signal.

    摘要翻译: 提供一种TD-SCDMA接收机,其包括从用于信号检测的信道估计块接收第一输入信号的联合检测(JD)块。 短信道检测(SCD)块基于来自信道估计块的第一输入信号接收第一输入信号并检测AGWN样信道的存在/不存在。 SCD块通过向JD块发送第二个输入信号来将JD块切换到1×和2×过采样率之间。

    ADVANCED JOINT DETECTION IN A TD-SCDMA SYSTEM
    3.
    发明申请
    ADVANCED JOINT DETECTION IN A TD-SCDMA SYSTEM 有权
    TD-SCDMA系统中的高级联合检测

    公开(公告)号:US20130070833A1

    公开(公告)日:2013-03-21

    申请号:US13235462

    申请日:2011-09-18

    IPC分类号: H04L27/06 H03K5/00

    摘要: A communication system is provided that includes a composite transfer module that receives an input signal and performs one or more selective operations defined by a first transfer function on the input signal. The composite transfer module outputs a first signal. A joint detection module receives the first signal and performs joint detection on the first signal. The joint detection module utilizes channel estimation information of the first transfer function so as to allow the joint detection module to perform joint detection with an oversampling rate of 2× or higher.

    摘要翻译: 提供了一种通信系统,其包括复合传送模块,其接收输入信号并执行由输入信号上的第一传递函数定义的一个或多个选择性操作。 复合传送模块输出第一信号。 联合检测模块接收第一信号并对第一信号进行联合检测。 联合检测模块利用第一传递函数的信道估计信息,以使联合检测模块以2×以上的过采样率进行联合检测。

    Advanced joint detection in a TD-SCDMA system
    4.
    发明授权
    Advanced joint detection in a TD-SCDMA system 有权
    TD-SCDMA系统高级联合检测

    公开(公告)号:US08711986B2

    公开(公告)日:2014-04-29

    申请号:US13235462

    申请日:2011-09-18

    IPC分类号: H04L27/06 H04B1/10

    摘要: A communication system is provided that includes a composite transfer module that receives an input signal and performs one or more selective operations defined by a first transfer function on the input signal. The composite transfer module outputs a first signal. A joint detection module receives the first signal and performs joint detection on the first signal. The joint detection module utilizes channel estimation information of the first transfer function so as to allow the joint detection module to perform joint detection with an oversampling rate of 2× or higher.

    摘要翻译: 提供了一种通信系统,其包括复合传送模块,其接收输入信号并执行由输入信号上的第一传递函数定义的一个或多个选择性操作。 复合传送模块输出第一信号。 联合检测模块接收第一信号并对第一信号进行联合检测。 联合检测模块利用第一传递函数的信道估计信息,以使联合检测模块以2×以上的过采样率进行联合检测。

    EFFICIENT IMPLEMENTATION OF JOINT DETECTION BASED TDSCDMA RECEIVERS
    5.
    发明申请
    EFFICIENT IMPLEMENTATION OF JOINT DETECTION BASED TDSCDMA RECEIVERS 审中-公开
    基于TDSCDMA接收机的联合检测的有效实现

    公开(公告)号:US20120269175A1

    公开(公告)日:2012-10-25

    申请号:US13092128

    申请日:2011-04-21

    IPC分类号: H04B7/216

    CPC分类号: H04B1/7105 H04B1/71055

    摘要: A TD-SCDMA receiver includes a joint detector that receives an input signal from a transceiver. The joint detector analyzes the input signal to determine whether one or more neighboring cells are used in conjunction with a servicing cell. Also, the joint detector assigns a first matrix that includes all coded channels including those associated with the one or neighboring cells so as to formulate a channel matrix. The joint detector uses a selective ratio that has been minimized to define elements of the first matrix so as to efficiently control the bit-width of the joint detector.

    摘要翻译: TD-SCDMA接收机包括从收发机接收输入信号的联合检测器。 联合检测器分析输入信号以确定一个或多个相邻单元是否与维修单元结合使用。 此外,联合检测器分配包括包括与一个或相邻小区相关联的所有编码信道的第一矩阵,以便制定信道矩阵。 联合检测器使用已经最小化的选择比来定义第一矩阵的元素,以便有效地控制关节检测器的位宽。

    ACTIVE CODE SELECTION FOR JOINT-DETECTION BASED TDSCDMA RECEIVER
    6.
    发明申请
    ACTIVE CODE SELECTION FOR JOINT-DETECTION BASED TDSCDMA RECEIVER 审中-公开
    基于联合检测的TDSCDMA接收机的主动代码选择

    公开(公告)号:US20120257548A1

    公开(公告)日:2012-10-11

    申请号:US13109009

    申请日:2011-05-17

    IPC分类号: H04L5/14 H04J13/00

    CPC分类号: H04B1/71052

    摘要: A TD-SCDMA receiver includes a joint detector that receives an input signal from a transceiver. The joint detector analyzes the input signal to using an active code selection (ACS) to determine whether one or more neighboring cells are used in conjunction with a servicing cell. Also, the ACS assigns a first matrix that includes necessary active coded channels including those associated with the one or neighboring cells so as to formulate a channel matrix.

    摘要翻译: TD-SCDMA接收机包括从收发机接收输入信号的联合检测器。 联合检测器分析输入信号以使用活动码选择(ACS)来确定一个或多个相邻小区是否与服务小区一起使用。 此外,ACS分配包括必需的活动编码信道的第一矩阵,包括与一个或相邻小区相关联的那些,以便制定信道矩阵。

    Architecture for joint detection hardware accelerator
    7.
    发明授权
    Architecture for joint detection hardware accelerator 有权
    联合检测硬件加速器架构

    公开(公告)号:US07953958B2

    公开(公告)日:2011-05-31

    申请号:US11818055

    申请日:2007-06-12

    IPC分类号: G06F15/76 G06F9/302

    摘要: A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

    摘要翻译: 联合检测系统被配置为执行接收信号的联合检测,并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值,中间结果和输出数据值的存储单元; 一个或多个计算单元,用于处理输入数据值和中间结果,并向存储器单元提供输出数据值; 控制器,用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元,简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器,矩阵存储器,主存储器和输出存储器。

    Architecture for joint detection hardware accelerator
    9.
    发明申请
    Architecture for joint detection hardware accelerator 有权
    联合检测硬件加速器架构

    公开(公告)号:US20080080468A1

    公开(公告)日:2008-04-03

    申请号:US11818055

    申请日:2007-06-12

    IPC分类号: H04B7/216

    摘要: A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

    摘要翻译: 联合检测系统被配置为执行接收信号的联合检测,并且包括联合检测加速器和主机处理器。 联合检测加速器可以包括用于存储输入数据值,中间结果和输出数据值的存储单元; 一个或多个计算单元,用于处理输入数据值和中间结果,并向存储器单元提供输出数据值; 控制器,用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。 计算单元可以包括复数乘法单元,简化复乘法累积单元和归一化浮点除法器。 存储器单元可以包括输入存储器,矩阵存储器,主存储器和输出存储器。

    Method and apparatus for joint detection
    10.
    发明授权
    Method and apparatus for joint detection 有权
    联合检测方法和装置

    公开(公告)号:US07916841B2

    公开(公告)日:2011-03-29

    申请号:US11545857

    申请日:2006-10-11

    IPC分类号: H04M1/64 H04L25/49

    CPC分类号: H04B1/7105 H04B2201/70711

    摘要: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

    摘要翻译: 提供联合检测系统及相关方法。 联合检测系统被配置为执行接收信号的联合检测,并且包括联合检测器加速器和可编程数字信号处理器(DSP)。 联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理,并输出从前端处理得到的第二数据。 联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。 可编程DSP耦合到联合检测器加速器,并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。 可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。