公开(公告)号：US07042798B2

公开(公告)日：2006-05-09

申请号：US10853313

申请日：2004-05-26

申请人： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

发明人： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

IPC分类号： G11C8/00

CPC分类号： G06F13/4243 ,  G11C11/406 ,  Y02D10/14 ,  Y02D10/151

摘要： It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.

摘要翻译： 旨在提供一种存储器控制装置和存储器控制方法，其能够在将各种命令输入到半导体存储器件中时减少所消耗的充电/放电电流并减少电力噪声的发生。 在时钟使能信号CKE处于活动状态的周期tCKE的一部分的时段TT 1，TT 2和TT 3期间，将控制时钟SD_CLK从存储器控制装置1提供给同步型半导体存储器件 12可以停止。 此外，在外部命令的数据输入/输出周期的输入和刷新命令RCMD的刷新操作周期的输入与外部命令的访问区域和刷新命令RCMD的访问区域不重合的情况下，这些命令 被并行地转换为控制指令信号SD_CMD，由此可以进行并行转换处理操作。

公开(公告)号：US20050157585A1

公开(公告)日：2005-07-21

申请号：US10853313

申请日：2004-05-26

申请人： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

发明人： Yoshiharu Kato ,  Gen Tsukishiro ,  Yoshihiro Takemae

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F13/42 ,  G11C8/00 ,  G11C11/406

CPC分类号： G06F13/4243 ,  G11C11/406 ,  Y02D10/14 ,  Y02D10/151

摘要： It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3 which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device 1 to a synchronous-type semiconductor memory device 12 can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.

摘要翻译： 旨在提供一种存储器控制装置和存储器控制方法，其能够在将各种命令输入到半导体存储器件中时减少所消耗的充电/放电电流并减少电力噪声的发生。 在时钟使能信号CKE处于活动状态的周期tCKE的一部分的时段TT 1，TT 2和TT 3期间，将控制时钟SD_CLK从存储器控制装置1提供给同步型半导体存储器件 12可以停止。 此外，在外部命令的数据输入/输出周期的输入和刷新命令RCMD的刷新操作周期的输入与外部命令的访问区域和刷新命令RCMD的访问区域不重合的情况下，这些命令 被并行地转换为控制指令信号SD_CMD，由此可以进行并行转换处理操作。

公开(公告)号：US20070241767A1

公开(公告)日：2007-10-18

申请号：US11812143

申请日：2007-06-15

申请人： Gen Tsukishiro

发明人： Gen Tsukishiro

IPC分类号： G01R31/26

CPC分类号： G01R31/31717 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

公开(公告)号：US08661198B2

公开(公告)日：2014-02-25

申请号：US13620521

申请日：2012-09-14

申请人： Gen Tsukishiro

发明人： Gen Tsukishiro

IPC分类号： G06F12/08

CPC分类号： G06F12/0804

摘要： A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.

摘要翻译： 一种插入在处理器和存储器件之间的缓存装置，包括：高速缓存存储器，用于存储来自存储器装置的数据; 保存从处理器输出的输出数据的缓冲器; 控制电路根据存取设备的请求确定高速缓存命中是否已经发生，并且如果发生高速缓存未命中，则响应于访问请求将输出数据存储在缓冲器中，输出 读取请求，用于从存储器件读取包含由访问请求请求的数据的行中的数据，将从存储器件的行输出的数据存储到高速缓冲存储器中，并将来自缓冲器的输出数据存储到高速缓冲存储器中。

公开(公告)号：US20060224923A1

公开(公告)日：2006-10-05

申请号：US11172928

申请日：2005-07-05

申请人： Gen Tsukishiro

发明人： Gen Tsukishiro

IPC分类号： G06F11/00

CPC分类号： G01R31/31717 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

公开(公告)号：US08380934B2

公开(公告)日：2013-02-19

申请号：US12706362

申请日：2010-02-16

申请人： Gen Tsukishiro

发明人： Gen Tsukishiro

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0804

摘要： A cache device interposed between a processor and a memory device, including: a cache memory storing data from the memory device; a buffer holding output data output from the processor; a control circuit determining, on the basis of a request to access the memory device, whether a cache hit has occurred or not and, if a cache miss has occurred, storing the output data in the buffer in response to the access request, outputting a read request for reading the data in a line containing data requested by the access request from the memory device, storing data output from the line of the memory device into the cache memory, and storing the output data from the buffer into the cache memory.

摘要翻译： 一种插入在处理器和存储器件之间的缓存装置，包括：高速缓存存储器，用于存储来自存储器装置的数据; 保存从处理器输出的输出数据的缓冲器; 控制电路根据存取设备的请求确定高速缓存命中是否已经发生，并且如果发生高速缓存未命中，则响应于访问请求将输出数据存储在缓冲器中，输出 读取请求，用于从存储器件读取包含由访问请求请求的数据的行中的数据，将从存储器件的行输出的数据存储到高速缓冲存储器中，并将来自缓冲器的输出数据存储到高速缓冲存储器中。

公开(公告)号：US07482830B2

公开(公告)日：2009-01-27

申请号：US11812143

申请日：2007-06-15

申请人： Gen Tsukishiro

发明人： Gen Tsukishiro

IPC分类号： G01R31/26

CPC分类号： G01R31/31717 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

摘要翻译： 一种用于测试包含产生第一和第二互补信号的控制器的半导体器件的方法以及根据第一和第二互补信号操作的存储器。 该方法包括将第一和第二互补信号选择性地切换到具有互补信号的中间电位的中间电位信号。 该方法还包括利用第一和第二互补信号和中间电位信号对第二装置进行操作测试。 该方法能够检测设备之间的有缺陷的连接。

公开(公告)号：US07248068B2

公开(公告)日：2007-07-24

申请号：US11172928

申请日：2005-07-05

申请人： Gen Tsukishiro

发明人： Gen Tsukishiro

IPC分类号： G01R31/26

CPC分类号： G01R31/31717 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate potential of the complementary signals. The method further includes conducting an operational test on the second device with the first and second complementary signals and the intermediate potential signal. This method enables detection of a defective connection between the devices.

摘要翻译： 一种用于测试包含产生第一和第二互补信号的控制器的半导体器件的方法以及根据第一和第二互补信号操作的存储器。 该方法包括将第一和第二互补信号选择性地切换到具有互补信号的中间电位的中间电位信号。 该方法还包括利用第一和第二互补信号和中间电位信号对第二装置进行操作测试。 该方法能够检测设备之间的有缺陷的连接。