公开(公告)号：US06369739B1

公开(公告)日：2002-04-09

申请号：US09427005

申请日：1999-10-26

申请人： Yoshihiro Inada ,  Shinji Yamashita

发明人： Yoshihiro Inada ,  Shinji Yamashita

IPC分类号： H03M112

CPC分类号： H04N9/68

摘要： The AGC circuit is provided with an analog variable gain amplifying circuit which includes a plurality of fixed gain amplifiers and a selector for selecting one of the output signals of the plurality of fixed gain amplifiers, an A/D converter for receiving the selected output signal from the variable gain amplifying circuit, a digital band pass filter which allows only the burst signal and the color signal in the output signal from the A/D converter to pass through, and a digital AGC/detection circuit for controlling the gain of the variable gain amplifying circuit such that the burst signal remains stable and for amplifying the digital signal to obtain a digital output color signal such that the detected burst signal becomes equal in level to the digital reference signal. Thus, a more stable output signal can be obtained even with the variation in the ambient temperature or the power supply voltage.

摘要翻译： AGC电路设置有模拟可变增益放大电路，其包括多个固定增益放大器和用于选择多个固定增益放大器的输出信号之一的选择器，A / D转换器，用于从 可变增益放大电路，仅允许来自A / D转换器的输出信号中的脉冲串信号和彩色信号通过的数字带通滤波器，以及用于控制可变增益的增益的数字AGC /检测电路 放大电路使得突发信号保持稳定并且用于放大数字信号以获得数字输出颜色信号，使得检测到的突发信号在数字参考信号的电平上变得相等。 因此，即使环境温度或电源电压的变化也能获得更稳定的输出信号。

公开(公告)号：US5296928A

公开(公告)日：1994-03-22

申请号：US025469

申请日：1993-03-03

申请人： Shinji Yamashita ,  Yoshihiro Inada

发明人： Shinji Yamashita ,  Yoshihiro Inada

IPC分类号： H04N5/10 ,  H04N5/08 ,  H04N5/04

CPC分类号： H04N5/08

摘要： A composite synchronizing signal separation circuit in which separation of the composite synchronizing signal by a digital circuit is realized and such trouble as adjusting the time constant is not needed and a phase shift is reduced: a horizontal interruption receiving circuit 1 which is reset by a timing pulse signal at the time point of 3/4 from the starting time point of one horizontal synchronizing period, and separates and outputs a horizontal synchronizing signal HD from a composite synchronizing signal SYNC; a schedule counter circuit 2 which is reset by the horizontal synchronizing signal HD and outputs count value while counting up to a predetermined value in one horizontal synchronizing period; a timing decoding circuit 3 which decodes the count value and respectively outputs timing pulse signals at the time points of 1/4, 1/2 and 3/4 from the starting time point of one horizontal synchronizing period; and a vertical interruption receiving circuit 4 which samples the composite synchronizing signal SYNC by these signals and outputs a vertical synchronizing signal VD.

摘要翻译： 一种复合同步信号分离电路，其中实现了由数字电路分离复合同步信号，并且不需要调整时间常数的问题，并且减少了相移：水平中断接收电路1由定时复位 从一个水平同步周期的开始时间点起的3/4的时间点的脉冲信号，并从复合同步信号SYNC分离并输出水平同步信号HD; 一个由水平同步信号HD复位的时间表计数器电路2，并且在一个水平同步周期中计数达预定值时输出计数值; 定时解码电路3，其从一个水平同步周期的起始时间点开始对该计数值进行解码并分别在1/4，1/2和3/4的时间点输出定时脉冲信号; 以及垂直中断接收电路4，其通过这些信号对复合同步信号SYNC进行采样，并输出垂直同步信号VD。

公开(公告)号：US5534807A

公开(公告)日：1996-07-09

申请号：US407652

申请日：1995-03-21

申请人： Yoshihiro Inada ,  Shinji Yamashita ,  Miki Nishimoto

发明人： Yoshihiro Inada ,  Shinji Yamashita ,  Miki Nishimoto

IPC分类号： H04N9/44 ,  H04N9/64 ,  H03H11/16

CPC分类号： H04N9/64

摘要： A sampling circuit is not susceptible to an influence of structural components and environmental changes. A phase difference detecting circuit (5) detects a deviation of a sampling clock (.phi.2) from optimal sampling timing and outputs a phase difference signal. On the other hand, a phase reference signal (ORG) which is used as a reference to determine a phase advance and a phase lag is generated by a phase reference detecting circuit (4). In accordance with these signals, a sampling clock shifting circuit (2) shifts the sampling clock (.phi.2) so that the sampling clock (.phi.2) is activated at optimal sampling timing. Sampling is performed in accordance with such a sampling clock (.phi.2), whereby a basic signal is generated from which the phase reference signal (ORG) and the phase difference signal (i.e., an equivalent signal (EQU) and a non-equivalent signal (UPDN)) are generated. By means of feedback control, the sampling clock is automatically activated at optimal sampling timing.

摘要翻译： 采样电路不受结构部件和环境变化的影响。 相位差检测电路（5）检测采样时钟（phi2）与最佳采样定时的偏差，并输出相位差信号。 另一方面，由相位参考检测电路（4）产生用作确定相位提前和相位滞后的基准的相位基准信号（ORG）。 根据这些信号，采样时钟移位电路（2）移位采样时钟（phi2），使得采样时钟（phi 2）在最佳采样定时被激活。 根据这样的采样时钟（phi 2）进行采样，由此产生基本信号，相位参考信号（ORG）和相位差信号（即，等效信号（EQU）和非等效信号 （UPDN））。 通过反馈控制，采样时钟在最佳采样时刻自动激活。

公开(公告)号：US5539343A

公开(公告)日：1996-07-23

申请号：US416212

申请日：1995-04-04

申请人： Shinji Yamashita ,  Yoshihiro Inada ,  Miki Nishimoto

发明人： Shinji Yamashita ,  Yoshihiro Inada ,  Miki Nishimoto

IPC分类号： H04N5/06 ,  H03L7/06

CPC分类号： H04N5/06

摘要： There is disclosed a horizontal synchronizing signal generating circuit for generating a horizontal synchronizing signal which has no frequency variations and which is in phase with an entered composite synchronizing signal if the entered composite synchronizing signal is a nonstandard signal having a varying horizontal frequency. A horizontal counter circuit (5) counts a reference clock (V.sub.CL), and a window pulse generating circuit (4) outputs a window pulse signal (V.sub.W) which is low for a fixed time period when a counter output (V.sub.CT) equals a counter value (878) indicative of a standard output timing. A horizontal synchronizing signal separating circuit (1) outputs a horizontal synchronizing signal (V.sub.2) only when the composite synchronizing signal (V.sub.1) falls within the fixed time period. Then a horizontal phase judging circuit (2) outputs a standard signal flag (V.sub.3) and a synchronizing signal generating circuit (3) outputs the horizontal synchronizing signal (V.sub.2) in synchronism with the reference clock (V.sub.CL). When the composite synchronizing signal (V.sub.1) does not fall within the fixed time period, the horizontal phase judging circuit (2) outputs a nonstandard signal flag (V.sub.3), and the synchronizing signal generating circuit (3) outputs a horizontal synchronizing signal (V.sub.4) produced from the window pulse signal (V.sub.W).

摘要翻译： 公开了一种水平同步信号发生电路，用于产生没有频率变化的水平同步信号，如果输入的复合同步信号是具有变化的水平频率的非标准信号，则与同步输入的复合同步信号相位。 水平计数器电路（5）对参考时钟（VCL）进行计数，并且窗口脉冲发生电路（4）在计数器输出（VCT）等于计数器时输出固定时间段内的低窗口脉冲信号（VW） 值（878）表示标准输出时序。 水平同步信号分离电路（1）仅在复合同步信号（V1）落入固定时间段内时输出水平同步信号（V2）。 然后，水平相位判断电路（2）输出标准信号标志（V3），并且同步信号发生电路（3）与参考时钟（VCL）同步地输出水平同步信号（V2）。 当复合同步信号（V1）不在固定时间段内时，水平相位判断电路（2）输出非标准信号标志（V3），同步信号发生电路（3）输出水平同步信号（V4 ）由窗口脉冲信号（VW）产生。

公开(公告)号：US5433910A

公开(公告)日：1995-07-18

申请号：US883338

申请日：1992-05-14

申请人： Hiroshi Mukai ,  Yasunobu Teramoto ,  Takahiko Sato ,  Yoshihiro Inada

发明人： Hiroshi Mukai ,  Yasunobu Teramoto ,  Takahiko Sato ,  Yoshihiro Inada

IPC分类号： B29C45/16

CPC分类号： B29C45/1642

摘要： A orifice passage for introducing excessive resin into a disposal tab forming cavity is provided at one end of a main cavity in a mold for sandwich molding. The section of the orifice passage is thinner in the central portion than in the opposite sides thereof. A thermoplastic elastomer for forming an outer layer of the molding is injected into the main cavity and then talc-containing polypropylene for forming the core of the molding is injected. The flow rate of the resins flowing through the orifice passage at this time becomes substantially uniform over the entirety of the section. Therefore, the talc-containing polypropylene sufficiently extends toward the opposite sides of the main cavity.

摘要翻译： 用于将多余树脂引入到处理片形成腔中的孔通道设置在用于夹层模制的模具中的主腔的一端。 孔口通道的部分在中部比在其相对侧更薄。 将用于形成模制品的外层的热塑性弹性体注入主腔中，然后注入用于形成模制芯的含滑石的聚丙烯。 此时流过孔口通道的树脂的流速在整个截面上变得基本均匀。 因此，含滑石的聚丙烯充分地向主腔的相对侧延伸。

公开(公告)号：US6103167A

公开(公告)日：2000-08-15

申请号：US907893

申请日：1997-08-11

申请人： Hiroshi Mukai ,  Yasunobu Teramoto ,  Yoshihiro Inada ,  Hirohisa Narukawa

发明人： Hiroshi Mukai ,  Yasunobu Teramoto ,  Yoshihiro Inada ,  Hirohisa Narukawa

IPC分类号： B29C45/16 ,  B29C45/73 ,  B29L31/30 ,  B60R13/04 ,  B29C35/00

CPC分类号： B60R13/04 ,  B29C45/1642 ,  B29C45/73 ,  B29C2045/7343

摘要： A sandwich molded article comprising a thick skin or outer layer, a thin skin or outer layer, and a core layer surrounded by these skins or outer layers. A process for producing said sandwich molded article by the use of a mold(s) which comprises adjusting the temperature of an inner surface of the mold corresponding to a skin portion of the molding desired to be made thick, to a temperature lower than that of an inner surface of the mold corresponding to a skin portion of the molding desired to be made thin; injecting a skin material in a softened state into the mold; and then injecting a core layer material in a softened state into the skin material. According to the present invention, there can be obtained a sandwich molded article having a core layer from which the distances to the obverse and the reverse of the molded article are different. This molded article can be given a satisfactory decorative surface and has deformation-preventing ability.

摘要翻译： 包含厚皮肤或外层，薄皮肤或外层以及由这些皮肤或外层包围的芯层的夹层模制品。 一种通过使用模具制造所述夹层模塑制品的方法，所述模具包括将所述模制品的皮肤部分的相应于所述模制品的皮肤部分的厚度的对应于所述厚度的模具的内表面的温度调节到低于 模具的内表面对应于期望制成薄的模制品的皮肤部分; 将软化状态的皮肤材料注入模具中; 然后将软化状态的芯层材料注入到皮肤材料中。 根据本发明，可以获得具有芯层的夹层模制品，模制品的正面和反面的距离与芯层不同。 该成形品能够赋予令人满意的装饰面，具有防变形能力。

公开(公告)号：US5254306A

公开(公告)日：1993-10-19

申请号：US782144

申请日：1991-10-28

申请人： Yoshihiro Inada ,  Hiroshi Mukai ,  Yasunobu Teramoto ,  Hiroshisa Narukawa

发明人： Yoshihiro Inada ,  Hiroshi Mukai ,  Yasunobu Teramoto ,  Hiroshisa Narukawa

IPC分类号： B29C45/16 ,  B29C45/17 ,  B29C45/27 ,  B29C45/38 ,  B29C45/28 ,  B29C45/30

CPC分类号： B29C45/1642 ,  B29C45/1704 ,  B29C2045/1718 ,  B29C45/2708 ,  B29C45/38

摘要： A mold for making a double layer molded product, such as a molded product of sandwich construction or a hollow molded product having a dam within the mold cavity adjacent its gate. The dam projects in a direction transverse to that in which the inner-forming material is injected, and a gap is defined between the dam and the walls of the cavity. With this configuration, the core thickness of the molded product of sandwich construction, or the skin thickness of the hollow molded product, are made uniform.

摘要翻译： 一种用于制造双层模制产品的模具，例如夹层结构的模制产品或具有在模腔内与其门相邻的坝的中空模制产品。 大坝在与内部成形材料注入的方向相反的方向上突出，并且在坝和壁的壁之间限定间隙。 利用这种构造，将夹层结构的模制产品的芯厚度或中空模制产品的表皮厚度均匀。

公开(公告)号：US06356145B1

公开(公告)日：2002-03-12

申请号：US09593933

申请日：2000-06-15

申请人： Yoshihiro Inada

发明人： Yoshihiro Inada

IPC分类号： H04N966

CPC分类号： H03D3/009 ,  H04N9/66

摘要： A demodulator circuit including: a signal generating circuit for generating a sine-wave signal and a cosine-wave signal whose frequencies are same as that of the carrier wave of a modulated signal, a multiplying circuit for multiplying the modulated signal by the sine-wave signal and the cosine-wave signal generated by the signal generating circuit, and a filtering circuit for eliminating the frequency twice as high as that of the carrier wave from each of the results of the computation conducted by the multiplying circuit. Due to this, no restriction is imposed by the frequency of the system clock signal in configuring the system as a whole.

摘要翻译： 一种解调器电路，包括：信号发生电路，用于产生正弦波信号和频率与调制信号的载波相同的余弦波信号;乘法电路，用于将调制信号乘以正弦波 信号和由信号发生电路产生的余弦波信号，以及滤波电路，用于从乘法电路进行的每个运算结果中消除两倍于载波的频率的频率。 因此，在整个系统配置中，不受系统时钟信号的频率的限制。

公开(公告)号：US5954784A

公开(公告)日：1999-09-21

申请号：US895379

申请日：1997-07-16

申请人： Yoshihiro Inada ,  Youichi Kishimoto

发明人： Yoshihiro Inada ,  Youichi Kishimoto

IPC分类号： G01M15/04 ,  F02D41/14 ,  F02D41/34 ,  F02D45/00 ,  F02P17/12 ,  G01M15/11 ,  F02P17/00 ,  G01M15/00

CPC分类号： F02D41/009 ,  F02D41/1498 ,  G01M15/11 ,  F02D2200/1015

摘要： Start points of a misfire determining interval in the cylinders of an engine are specified by counting Pos signals starting from the appearance of a Ref signal in a specific cylinder. The Pos signals output from the Ref signal in each cylinder to the start point of the misfire determining interval are also counted as RGPHS after engine startup, and a shift of the misfire determining interval is detected by comparing for example the sum total of RGPHS for all cylinders and the sum total on the immediately preceding occasion. Correction of the misfire determining interval by a learnt value is stopped according to this shift. Preferably, correction of the misfire determining interval by the learnt value is restarted after making all misfire determining intervals the same by correcting for the shift.

摘要翻译： 通过从特定气缸中的Ref信号的出现开始计数Pos信号来指定发动机气缸中的失火判定间隔的起点。 从每个气缸中的Ref信号输出到失火判定间隔的起始点的Pos信号在发动机启动后也被计入RGPHS，并且通过比较例如所有的RGPHS的总和来检测失火判定间隔的偏移 气瓶和前一时刻的总和。 根据该偏移，停止通过学习值对失火判定间隔进行校正。 优选地，通过校正偏移量使得所有失火确定间隔相同之后，通过学习值校正失火确定间隔。

公开(公告)号：US5920008A

公开(公告)日：1999-07-06

申请号：US768198

申请日：1996-12-17

申请人： Youichi Kishimoto ,  Yoshihiro Inada

发明人： Youichi Kishimoto ,  Yoshihiro Inada

IPC分类号： G01M15/04 ,  F02D45/00 ,  G01M15/11 ,  G01M15/00

CPC分类号： G01M15/11

摘要： A diagnostic apparatus applicable to diagnosis of engine misfire. A diagnostic result is produced for each of at least two diagnoses related to each other. Only one of the diagnostic results having a higher degree of necessity is retained to indicate a malfunction.

摘要翻译： 适用于诊断发动机失火的诊断装置。 对于彼此相关的至少两个诊断中的每一个产生诊断结果。 只有一个具有较高程度的诊断结果被保留以指示故障。