公开(公告)号：US06849550B2

公开(公告)日：2005-02-01

申请号：US10190756

申请日：2002-07-09

申请人： Yoshinari Ichihashi ,  Norihiro Ikeda ,  Takashi Gotou ,  Ryousuke Usui ,  Tatsuya Fujishima

发明人： Yoshinari Ichihashi ,  Norihiro Ikeda ,  Takashi Gotou ,  Ryousuke Usui ,  Tatsuya Fujishima

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/485

摘要： A method for manufacturing a semiconductor device that forms a connection hole with high electric reliability even when the semiconductor device is designed to be highly integrated. The semiconductor device includes a lower layer wiring and an interlayer insulation film, which is formed on the lower layer wiring and has a connection hole connected with the lower layer wiring. The method includes forming the connection hole by etching the interlayer insulation film. The connection hole is formed by etching part of the lower layer wiring under a first etching condition through physical reaction in at least the vicinity of the lower layer wiring, and by etching part of the interlayer insulation film under a second etching condition that guarantees a selective ratio relative to the lower layer wiring.

摘要翻译： 即使半导体器件设计为高度集成，也可以形成具有高电可靠性的连接孔的半导体器件的制造方法。 半导体器件包括下层布线和层间绝缘膜，其形成在下层布线上并具有与下层布线连接的连接孔。 该方法包括通过蚀刻层间绝缘膜形成连接孔。 在第一蚀刻条件下，至少在下层布线附近通过物理反应蚀刻下层布线的一部分，并且在保证选择性的第二蚀刻条件下蚀刻层间绝缘膜的一部分，形成连接孔 相对于下层布线的比例。