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1.发明申请Bus control system for integrated circuit device with improved bus access efficiency 有权集成电路设备总线控制系统，提高总线访问效率公开(公告)号：US20050223151A1
公开(公告)日：2005-10-06
申请号：US11136417
申请日：2005-05-25
CPC分类号： G06F13/126 , G06F9/3879
摘要： The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.
摘要翻译： 本发明是在LSI发出命令或数据（发行侧LSI）的两个集成电路装置（以下称为LSI）之间的命令或数据传送，其将指示有效的命令或数据被发送的选通信号输出到LSI 其接收命令或数据（接收侧LSI），并且接收侧LSI将通知命令处理完成的信号（命令就绪信号）输出到发行侧LSI。 发行方LSI包括计数器，其中指示接收侧LSI可以同时处理或同时接收的命令数的值在初始化时被加载，其中当发出命令或数据时计数器递减，当计数器递增时，计数器递增 接收就绪信号，并且当计数器变为“0”时禁止发出命令或数据。 因此，发行方LSI可以向接收侧LSI发出命令或数据，而不确认来自接收侧LSI的忙信号。
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2.发明授权Bus control system for integrated circuit device with improved bus access efficiency 有权集成电路设备总线控制系统，提高总线访问效率公开(公告)号：US07349998B2
公开(公告)日：2008-03-25
申请号：US11136417
申请日：2005-05-25
IPC分类号： G06F3/00
CPC分类号： G06F13/126 , G06F9/3879
摘要： The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.
摘要翻译： 本发明是在LSI发出命令或数据（发行侧LSI）的两个集成电路装置（以下称为LSI）之间的命令或数据传送，其将指示有效的命令或数据被发送的选通信号输出到LSI 其接收命令或数据（接收侧LSI），并且接收侧LSI将通知命令处理完成的信号（命令就绪信号）输出到发行侧LSI。 发行方LSI包括计数器，其中指示接收侧LSI可以同时处理或同时接收的命令数的值在初始化时被加载，其中当发出命令或数据时计数器递减，当计数器递增时，计数器递增 接收就绪信号，并且当计数器变为“0”时禁止发出命令或数据。 因此，发行方LSI可以向接收侧LSI发出命令或数据，而不确认来自接收侧LSI的忙信号。
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3.发明授权Bus control system for integrated circuit device with improved bus access efficiency 有权集成电路设备总线控制系统，提高总线访问效率公开(公告)号：US06917995B2
公开(公告)日：2005-07-12
申请号：US09739835
申请日：2000-12-20
CPC分类号： G06F13/126 , G06F9/3879
摘要： The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIS) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.
摘要翻译： 本发明是两个集成电路装置（以下称为LSIS）之间的命令或数据传送，其中发出命令或数据（发行方LSI）的LSI将指示有效命令或数据被发送的选通信号输出到LSI 其接收命令或数据（接收侧LSI），并且接收侧LSI将通知命令处理完成的信号（命令就绪信号）输出到发行侧LSI。 发行方LSI包括计数器，其中指示接收侧LSI可以同时处理或同时接收的命令数的值在初始化时被加载，其中当发出命令或数据时计数器递减，当计数器递增时，计数器递增 接收就绪信号，并且当计数器变为“0”时禁止发出命令或数据。 因此，发行方LSI可以向接收侧LSI发出命令或数据，而不确认来自接收侧LSI的忙信号。
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4.发明申请公开(公告)号：US20050220661A1
公开(公告)日：2005-10-06
申请号：US11085392
申请日：2005-03-21
CPC分类号： H01H37/76
摘要： An In—Sn alloy of 85 to 52% In provides advantages that dispersion of an operating temperature can be sufficiently eliminated, and that a high yield can be ensured by adequate ductility, but has a defect which is fatal to a DC fuse, or in which troubles due to long-term DC application such as long-term DC application breakage occurs. In view of this fact, when an alloy type thermal fuse in which an In—Sn alloy is used as a fuse element is used under DC application, stability under long-term DC application that is a condition severer than that under AC application is imposed on the alloy type thermal fuse, whereby the fuse can be rationally used. An AC electronic/electrical appliance is protected against overheating by an AC-only alloy type thermal fuse in which a fuse element is made of an In—Sn alloy, and which has a predetermined operating temperature, and a DC electronic/electrical appliance is protected against overheating of a same temperature by a DC alloy type thermal fuse in which the alloy composition of a fuse element is different from that of the AC-only alloy type thermal fuse.
摘要翻译： 85〜52％In的In-Sn合金可以充分消除工作温度的分散，通过充分的延展性可以确保高产率，但是具有对直流熔断器致命的缺陷，或 由于长期直流应用破坏等长期直流应用引起的故障。 鉴于这一事实，当在直流应用下使用其中使用In-Sn合金的合金型热熔丝时，施加比在AC施加下更严格的条件下的长期DC施加下的稳定性 在合金型热熔丝上，可以合理使用保险丝。 AC电子电器通过仅由合金型的热熔丝保护而不被过热，其中熔丝元件由In-Sn合金制成，并具有预定的工作温度，并且DC电子电器被保护 通过熔丝元件的合金组成不同于仅合金型热熔丝的合金组成的DC合金型热熔丝来防止相同温度的过热。
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5.发明授权Break determining circuit for a debugging support unit in a semiconductor integrated circuit 失效用于半导体集成电路中的调试支持单元的断开确定电路公开(公告)号：US06877113B2
公开(公告)日：2005-04-05
申请号：US10101777
申请日：2002-03-21
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A semiconductor integrated circuit including a debugging support unit and a buffer memory for temporarily storing trace data, the debugging support unit comprising a break detection member that detects a break signal externally inputted and a break determining member that determines whether the break signal requests to shift to break processing after outputting all the trace data stored in the buffer memory or the break signal requests to shift to the break processing with immediately suspending trace data outputting.
摘要翻译： 一种半导体集成电路，包括用于临时存储跟踪数据的调试支持单元和缓冲存储器，所述调试支持单元包括检测外部输入的中断信号的中断检测构件和判断所述中断信号是否转移到 在输出存储在缓冲存储器中的所有跟踪数据之后的中断处理或者中断信号请求以立即挂起跟踪数据输出来转移到中断处理。
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公开(公告)号：US06841845B2
公开(公告)日：2005-01-11
申请号：US10616087
申请日：2003-07-08
CPC分类号： C22C28/00 , H01H37/761 , H01H2037/768 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： An alloy type thermal fuse is provided in which, although a fuse element essentially comprising an In-Sn alloy is used, the operation stability to a heat cycle can be satisfactorily assured, and, even when the amount of In is large, a process of drawing to the fuse element at a high yield can be ensured, and which has an operating temperature belonging to the range of 120 to 150° C. The fuse element has an alloy composition in which 0.1 to 7 weight parts of one, or two or more metals selected from the group consisting of Ag, Au, Cu, Ni, Pd, Pt, and Sb are added to 100 weight parts of an alloy of 52 to 85% In and a balance Sn.
摘要翻译： 提供了一种合金型热熔丝，其中，尽管使用了基本上包含In-Sn合金的熔丝元件，但是可以令人满意地确保对热循环的操作稳定性，并且即使当In的量大时， 可以确保以高产率拉入保险丝元件，并且具有属于120至150℃范围的工作温度。熔丝元件具有合金组成，其中0.1至7重量份的一个或两个或 在100重量份的合金中添加选自Ag，Au，Cu，Ni，Pd，Pt和Sb的更多的金属，并且其余为Sn。
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公开(公告)号：US06775718B2
公开(公告)日：2004-08-10
申请号：US09933765
申请日：2001-08-22
IPC分类号： G06F1328
CPC分类号： G06F13/28
摘要： A direct memory access control system supplies the respective status signals indicating timings of the read data effective state or writable state between the input/output interface and memory interface, both interfaces maintain the read data effective state and writable state of the input/output memory and synchronous memory under control until the later timing comes up. Consequently, it is possible to match the read data effective timing and writable timing of the synchronous memory and input/output memory, thus making possible flyby transfer of data between both memories.
摘要翻译： 直接存储器访问控制系统提供指示输入/输出接口和存储器接口之间的读取数据有效状态或可写状态的定时的相应状态信号，两个接口保持读取数据有效状态和输入/输出存储器的可写状态，以及 同步存储器被控制，直到稍后的时间到来。 因此，可以将同步存储器和输入/输出存储器的读取数据有效定时和可写入定时相匹配，从而使得两个存储器之间的数据可能的飞越传输。
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8.发明授权Semiconductor integrated circuit, operating method of semiconductor integrated circuit, and debug system 有权半导体集成电路，半导体集成电路的操作方法和调试系统公开(公告)号：US08595562B2
公开(公告)日：2013-11-26
申请号：US13014318
申请日：2011-01-26
申请人： Takashi Sato , Toshiaki Saruwatari , Ken Ryu
发明人： Takashi Sato , Toshiaki Saruwatari , Ken Ryu
IPC分类号： G06F11/00
CPC分类号： G01R31/28 , G06F1/26 , G06F11/24 , G06F11/3024 , G06F11/3062 , G06F11/3636 , G06F11/3648
摘要： A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced.
摘要翻译： 电流测量单元，测量在多个电路块中消耗的电源电流，其中至少一个电路块包括处理器，并输出测量结果作为电源电流值。 选择单元根据选择信息选择电源电流值中的至少一个。 顺序地保持由选择单元选择的电源电流值与跟随执行信息的跟踪缓冲器，并顺序地输出保持的信息。 通过根据选择信息选择调试所需的电路块的电源电流值，可以减少包括跟踪电源电流值的调试所需的半导体集成电路的外部端子的数量。 结果，可以减少具有调试功能的半导体集成电路的芯片尺寸。
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公开(公告)号：US06963264B2
公开(公告)日：2005-11-08
申请号：US10608478
申请日：2003-06-27
CPC分类号： C22C13/02 , C22C12/00 , C22C30/04 , H01H37/761 , H01H2037/768
摘要： The invention relates to an alloy type thermal fuse and a wire member for a thermal fuse element, and provides an alloy type thermal fuse in which a fuse element does not contain a harmful metal, the operating temperature is about 150° C., the dispersion of the operating temperature can be sufficiently suppressed, and the operation stability to a heat cycle can be satisfactorily assured. The thermal fuse has an alloy composition of 30 to 70% Sn, 0.3 to 20% Sb, and a balance Bi.
摘要翻译： 本发明涉及一种合金型热熔丝和用于热熔丝元件的线材，并提供一种合金型热熔丝，其中熔丝元件不含有害金属，工作温度约为150℃，分散体 可以充分地抑制工作温度，并且能够令人满意地确保对热循环的操作稳定性。 热熔丝具有30〜70％Sn，0.3〜20％Sb，余量为Bi的合金组成。
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公开(公告)号：US20050128044A1
公开(公告)日：2005-06-16
申请号：US10954765
申请日：2004-09-30
CPC分类号： C22C28/00 , H01H37/761 , H01H2037/768
摘要： An alloy type thermal fuse is provided in which, although a fuse element essentially comprising an In—Sn alloy is used, shear breakage at the melting point or lower can be prevented from occurring even under long-term DC application, the operation stability to a heat cycle can be satisfactorily assured, and a process of drawing to the fuse element at a high yield can be ensured, and which has an operating temperature belonging to the range of 120 to 150° C. As a metal element for preventing long-term DC breakage which prevents the fuse element from being broken under long-term DC application, Cu is added to an In—Sn composition of 52 to 85% In and a balance Sn.
摘要翻译： 提供了一种合金型热熔丝，其中，尽管使用了基本上包含In-Sn合金的熔丝元件，但是即使在长期直流施加下也可以防止在熔点或更低熔点下的剪切断裂，对 可以令人满意地确保热循环，并且可以确保以高产率拉入熔丝元件的工艺，其工作温度属于120-150℃。作为防止长期使用的金属元件 DC断裂，其防止熔丝元件在长期DC施加下被破坏，Cu被添加到In-Sn组成为52至85％In且余量为Sn。
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