公开(公告)号：US20080133985A1

公开(公告)日：2008-06-05

申请号：US11968664

申请日：2008-01-03

申请人： Yoshiro RIHO ,  Yutaka Ito

发明人： Yoshiro RIHO ,  Yutaka Ito

IPC分类号： G11C29/08 ,  G06F11/26

CPC分类号： G06F11/1076 ,  G06F11/1012 ,  G11C11/406 ,  G11C29/42 ,  G11C2211/4062

摘要： A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

摘要翻译： 一种半导体器件的测试方法，该半导体器件设置有使用由第一代码组成的产品代码和用于实现存储器的错误校正的第二代码的ECC电路，该测试方法包括以下步骤：获得第一通过/不确定 分别通过基于第一代码和第二代码的独立校正操作实现的结果和第二通过/失败确定结果; 将结果分别记录在第一故障存储器和第二故障存储器中; 执行诸如与第一故障存储器的内容和第二故障存储器的内容有关的AND操作的规定的逻辑操作; 并基于逻辑运算的结果，纠正故障位和潜在故障位。

公开(公告)号：US07346829B2

公开(公告)日：2008-03-18

申请号：US11092706

申请日：2005-03-30

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： H03M13/00

CPC分类号： G06F11/1076 ,  G06F11/1012 ,  G11C11/406 ,  G11C29/42 ,  G11C2211/4062

摘要： A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

摘要翻译： 一种半导体器件的测试方法，该半导体器件设置有使用由第一代码组成的产品代码和用于实现存储器的错误校正的第二代码的ECC电路，该测试方法包括以下步骤：获得第一通过/不确定 分别通过基于第一代码和第二代码的独立校正操作实现的结果和第二通过/失败确定结果; 将结果分别记录在第一故障存储器和第二故障存储器中; 执行诸如与第一故障存储器的内容和第二故障存储器的内容有关的AND操作的规定的逻辑操作; 并基于逻辑运算的结果，纠正故障位和潜在故障位。

公开(公告)号：US07529986B2

公开(公告)日：2009-05-05

申请号：US11968664

申请日：2008-01-03

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： G11C29/00 ,  G11C7/00 ,  H03M13/00

CPC分类号： G06F11/1076 ,  G06F11/1012 ,  G11C11/406 ,  G11C29/42 ,  G11C2211/4062

摘要： A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

摘要翻译： 一种半导体器件的测试方法，该半导体器件设置有使用由第一代码组成的产品代码和用于实现存储器的错误校正的第二代码的ECC电路，该测试方法包括以下步骤：获得第一通过/不确定 分别通过基于第一代码和第二代码的独立校正操作实现的结果和第二通过/失败确定结果; 将结果分别记录在第一故障存储器和第二故障存储器中; 执行诸如与第一故障存储器的内容和第二故障存储器的内容有关的AND操作的规定的逻辑操作; 并基于逻辑运算的结果，纠正故障位和潜在故障位。

公开(公告)号：US07355919B2

公开(公告)日：2008-04-08

申请号：US11806438

申请日：2007-05-31

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/40626 ,  G06F11/1004 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

摘要翻译： 动态半导体存储装置，其中待机时间期间的电源电流减小以降低功耗并且抑制芯片面积增加。 在正常操作期间，关于与正常操作期间访问的行地址相关联的字线的信息被存储在RAM中。 在进入自刷新时，读出连接到与正常操作时间期间访问的行地址相关联的字线的存储器单元的数据，并将数据的校验位附加到编码器中并写入校验位区域。 作为上电顺序后的第一自刷新输入的初始化动作，对每个字线检查存储单元的数据保持时间。 基于检查结果，确定字线的刷新周期的设定值并写入RAM中，以设定基于字线的刷新周期。 在错误检查刷新操作期间，错误校正电路校正任何错误。

公开(公告)号：US20070230265A1

公开(公告)日：2007-10-04

申请号：US11806438

申请日：2007-05-31

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/40626 ,  G06F11/1004 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

公开(公告)号：US20050229076A1

公开(公告)日：2005-10-13

申请号：US11092706

申请日：2005-03-30

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： H03M13/01 ,  G06F11/00 ,  G06F11/10 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4078 ,  G11C29/00 ,  G11C29/42 ,  H03M13/00 ,  H03M13/29

CPC分类号： G06F11/1076 ,  G06F11/1012 ,  G11C11/406 ,  G11C29/42 ,  G11C2211/4062

摘要： A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

摘要翻译： 一种半导体器件的测试方法，该半导体器件设置有使用由第一代码组成的产品代码和用于实现存储器的错误校正的第二代码的ECC电路，该测试方法包括以下步骤：获得第一通过/不确定 分别通过基于第一代码和第二代码的独立校正操作实现的结果和第二通过/失败确定结果; 将结果分别记录在第一故障存储器和第二故障存储器中; 执行诸如与第一故障存储器的内容和第二故障存储器的内容有关的AND操作的规定的逻辑操作; 并基于逻辑运算的结果，纠正故障位和潜在故障位。

公开(公告)号：US07260011B2

公开(公告)日：2007-08-21

申请号：US11640388

申请日：2006-12-18

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/40626 ,  G06F11/1004 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

公开(公告)号：US20070097772A1

公开(公告)日：2007-05-03

申请号：US11640388

申请日：2006-12-18

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/40626 ,  G06F11/1004 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

公开(公告)号：US07167403B2

公开(公告)日：2007-01-23

申请号：US11042441

申请日：2005-01-26

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/40626 ,  G06F11/1004 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

摘要翻译： 动态半导体存储装置，其中待机时间期间的电源电流减小以降低功耗并且抑制芯片面积增加。 在正常操作期间，关于与正常操作期间访问的行地址相关联的字线的信息被存储在RAM中。 在进入自刷新时，读出连接到与正常操作时间期间访问的行地址相关联的字线的存储器单元的数据，并将数据的校验位附加到编码器中并写入校验位区域。 作为上电顺序后的第一自刷新输入的初始化动作，对每个字线检查存储单元的数据保持时间。 基于检查结果，确定字线的刷新周期的设定值并写入RAM中，以设定基于字线的刷新周期。 在错误检查刷新操作期间，错误校正电路校正任何错误。

公开(公告)号：US07158433B2

公开(公告)日：2007-01-02

申请号：US11097247

申请日：2005-04-04

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/401 ,  G11C11/40615 ,  G11C29/02 ,  G11C29/023 ,  G11C29/50016 ,  G11C2211/4061 ,  G11C2211/4068

摘要： A semiconductor storage device having a memory cell array in which a plurality of memory cells is provided at intersections of a plurality of bit lines and a plurality of word lines and executing refreshing for holding data, including: memory cells for pairing provided on the memory cell array, for compensating for errors of each memory cell; a control circuit for checking a data holding ability of memory cell under test in a predetermined period after power-on; a storage circuit for storing information which specifies the memory cells under test for which it is determined that the data holding ability is low in the checking of the control circuit; and a selecting-line activating circuit for activating circuit for activating a selecting line for pairing corresponding to the memory cells for pairing based on a result of comparing a specific address to be input with the information stored in the storage circuit.

摘要翻译： 一种具有存储单元阵列的半导体存储装置，其中在多个位线和多个字线的交叉点处设置多个存储单元，并执行用于保持数据的刷新，所述存储单元阵列包括：用于配置在存储单元上的存储单元 阵列，用于补偿每个存储单元的误差; 控制电路，用于在上电之后的预定时间段内检查被测试的存储器单元的数据保持能力; 存储电路，用于存储确定在检查控制电路时数据保持能力较低的被测试存储单元的信息; 以及选择线激活电路，用于基于将要输入的特定地址与存储在存储电路中的信息进行比较的结果，激活用于激活与用于配对的存储器单元相对应的配对的选择线的电路。