公开(公告)号：US20120241856A1

公开(公告)日：2012-09-27

申请号：US13486738

申请日：2012-06-01

申请人： Yoshito NAKAZAWA ,  Yuji YATSUDA

发明人： Yoshito NAKAZAWA ,  Yuji YATSUDA

IPC分类号： H01L29/78

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成功率MISFET的源极区域和保护二极管的n +型半导体区域。