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公开(公告)号：US20120049901A1
公开(公告)日：2012-03-01
申请号：US13217578
申请日：2011-08-25
CPC分类号： H03K19/0016
摘要： An object of the invention is to reduce the power consumption of a semiconductor device that requires a plurality of reference potentials and a method of driving the semiconductor device. Disclosed is a semiconductor device having a potential divider circuit in which a potential supplied to a power supply line is resistively divided by resistors connected in series to the power supply line so that a desired potential is output through a switch transistor electrically connected to the power supply line. A drain terminal of the switch transistor is electrically connected to a gate terminal of a transistor provided in a circuit on the output side (or to one terminal of a capacitor) to form a node. The switch transistor has an off current low enough to hold the desired voltage in the node even when the potential is no more supplied to the power supply line.
摘要翻译： 本发明的目的是降低需要多个参考电位的半导体器件的功耗以及驱动半导体器件的方法。 公开了一种具有分压器电路的半导体器件，其中提供给电源线的电位被电阻器电阻分压，电阻器与电源线串联连接，从而通过电连接到电源的开关晶体管输出期望的电位 线。 开关晶体管的漏极端子电连接到设置在输出侧（或电容器的一个端子）的电路中的晶体管的栅极端子，以形成节点。 开关晶体管具有足够低的关断电流，以便即使当电势不再供应到电源线时，也能够在节点中保持期望的电压。
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公开(公告)号：US08952728B2
公开(公告)日：2015-02-10
申请号：US13217578
申请日：2011-08-25
CPC分类号： H03K19/0016
摘要： An object of the invention is to reduce the power consumption of a semiconductor device that requires a plurality of reference potentials and a method of driving the semiconductor device. Disclosed is a semiconductor device having a potential divider circuit in which a potential supplied to a power supply line is resistively divided by resistors connected in series to the power supply line so that a desired potential is output through a switch transistor electrically connected to the power supply line. A drain terminal of the switch transistor is electrically connected to a gate terminal of a transistor provided in a circuit on the output side (or to one terminal of a capacitor) to form a node. The switch transistor has an off current low enough to hold the desired voltage in the node even when the potential is no more supplied to the power supply line.
摘要翻译： 本发明的目的是降低需要多个参考电位的半导体器件的功耗以及驱动半导体器件的方法。 公开了一种具有分压器电路的半导体器件，其中提供给电源线的电位被电阻器电阻分压，电阻器与电源线串联连接，从而通过电连接到电源的开关晶体管输出期望的电位 线。 开关晶体管的漏极端子电连接到设置在输出侧（或电容器的一个端子）的电路中的晶体管的栅极端子，以形成节点。 开关晶体管具有足够低的关断电流，以便即使当电势不再供应到电源线时，也能够在节点中保持期望的电压。
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公开(公告)号：US08779799B2
公开(公告)日：2014-07-15
申请号：US13467500
申请日：2012-05-09
申请人： Yoshiya Takewaki
发明人： Yoshiya Takewaki
CPC分类号： H03K19/017581 , H03K19/0948 , H03K19/1776 , H03K19/17772
摘要： A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.
摘要翻译： 提供一种逻辑电路，即使在未提供电源电位时也能够保持逻辑电路的开关状态，在供电之后逻辑块的启动时间短，可以以低功耗工作，并且可以 容易地在NAND电路和NOR电路之间切换。 在NAND电路和NOR电路之间的切换是通过包括氧化物半导体的晶体管切换节点处的电荷保持状态来实现的。 通过使用作为晶体管的宽带隙半导体的氧化物半导体材料，可以充分降低晶体管的截止电流; 因此，在节点处保持的电荷状态可以是非易失性的。
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公开(公告)号：US09001563B2
公开(公告)日：2015-04-07
申请号：US13455188
申请日：2012-04-25
申请人： Tomoaki Atsumi , Yoshiya Takewaki
发明人： Tomoaki Atsumi , Yoshiya Takewaki
IPC分类号： G11C11/24 , G11C11/404 , G11C11/401 , G11C11/4099 , H01L27/12 , H01L27/108
CPC分类号： G11C5/10 , G11C11/401 , G11C11/404 , G11C11/406 , G11C11/4091 , G11C11/4099 , H01L27/10873 , H01L27/10897 , H01L27/1218 , H01L27/1225
摘要： In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.
摘要翻译： 在包括具有排列成矩阵的存储单元的存储单元阵列的存储器模块中，每个存储单元包括使用氧化物半导体的第一晶体管和第一电容器; 包括p沟道第三晶体管，第二电容器和使用氧化物半导体的第二晶体管的参考单元; 以及包括电阻器和比较器的刷新定时检测电路，其中当通过第一晶体管向第一电容器提供电位时，通过第二晶体管将电位提供给第二电容器，其中第三晶体管的漏极电流值 根据存储在第二电容器中的电位而改变，并且当第三晶体管的漏极电流值高于给定值时，执行存储单元阵列和参考单元的刷新操作。
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