公开(公告)号：US08278177B2

公开(公告)日：2012-10-02

申请号：US13240303

申请日：2011-09-22

申请人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

发明人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

摘要翻译： 在沟槽中通过外延生长法形成第一p型SiGe混晶层，形成第二p型SiGe混晶层。 在第二SiGe混晶层上形成第三p型SiGe混晶层。 从沟槽底部开始的第一SiGe混合晶体层的最上表面的高度低于沟槽的深度，硅衬底的表面是标准的。 从沟槽底部开始的第二SiGe混合晶体层的最上表面的高度高于沟槽的深度，硅衬底的表面是标准的。 第一和第三SiGe混晶层中的Ge浓度低于第二SiGe混晶层中的Ge浓度。

公开(公告)号：US20120329229A1

公开(公告)日：2012-12-27

申请号：US13603577

申请日：2012-09-05

申请人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

发明人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

公开(公告)号：US20110049533A1

公开(公告)日：2011-03-03

申请号：US12916953

申请日：2010-11-01

申请人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L29/24

CPC分类号： H01L29/165 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

摘要翻译： 公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。 在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。 当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和 硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。

公开(公告)号：US08518785B2

公开(公告)日：2013-08-27

申请号：US13603577

申请日：2012-09-05

申请人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

发明人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

公开(公告)号：US07875521B2

公开(公告)日：2011-01-25

申请号：US12458621

申请日：2009-07-17

申请人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L21/336

CPC分类号： H01L29/165 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

摘要翻译： 公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。 在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。 当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和 硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。

公开(公告)号：US20100129971A1

公开(公告)日：2010-05-27

申请号：US12698303

申请日：2010-02-02

申请人： Hiroyuki Ohta ,  Takashi Sakuma ,  Yosuke Shimamune ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Hiroyuki Ohta ,  Takashi Sakuma ,  Yosuke Shimamune ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

摘要翻译： 公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。 在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。 当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和 硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。

公开(公告)号：US07683362B2

公开(公告)日：2010-03-23

申请号：US11471732

申请日：2006-06-21

申请人： Hiroyuki Ohta ,  Takashi Sakuma ,  Yosuke Shimamune ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Hiroyuki Ohta ,  Takashi Sakuma ,  Yosuke Shimamune ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L31/00

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

摘要翻译： 公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。 在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。 当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和 硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。

公开(公告)号：US20090280612A1

公开(公告)日：2009-11-12

申请号：US12458621

申请日：2009-07-17

申请人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L21/336 ,  H01L21/36

CPC分类号： H01L29/165 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

公开(公告)号：US20070126036A1

公开(公告)日：2007-06-07

申请号：US11393656

申请日：2006-03-31

申请人： Hiroyuki Ohta ,  Akiyoshi Hatada ,  Yosuke Shimamune ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Hiroyuki Ohta ,  Akiyoshi Hatada ,  Yosuke Shimamune ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device is configured so that there is formed a stressor film 4 covering the first field effect transistor and the second field effect transistor, formed with openings from which the originating area and the terminating area of each of the first field effect transistor and the second field effect transistor are partially exposed, and applying a stress to at least an area extending from the vicinity of the originating area to the vicinity of the terminating area of each of the first field effect transistor and the second field effect transistor, and that a height of a first gate electrode 3 (3A) in a direction substantially perpendicular to a first insulating layer is set different from a height of a second electrode 3 (3B) in the direction substantially perpendicular to a second insulating layer.

摘要翻译： 半导体器件被配置为使得形成有覆盖第一场效应晶体管和第二场效应晶体管的应力器膜4，第一场效应晶体管和第二场效应晶体管形成有开口，第一场效应晶体管和第二场效应晶体管的起始区域和终止区域从该开口 场效应晶体管部分露出，并且对至少从始发区域附近延伸到第一场效应晶体管和第二场效应晶体管的端接区域附近的区域施加应力， 在基本上垂直于第一绝缘层的方向上的第一栅电极3（3A）的设置与第二电极3（3B）的高度基本上垂直于第二绝缘层的方向设定。

公开(公告)号：US20070012913A1

公开(公告)日：2007-01-18

申请号：US11471732

申请日：2006-06-21

申请人： Hiroyuki Ohta ,  Takashi Sakuma ,  Yosuke Shimamune ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Hiroyuki Ohta ,  Takashi Sakuma ,  Yosuke Shimamune ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L31/00

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

摘要翻译： 公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。 在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。 当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和 硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。