公开(公告)号：US09709377B2

公开(公告)日：2017-07-18

申请号：US14396399

申请日：2012-04-23

Applicant: Hiroyuki Ohta ,  Kisho Ashida

Inventor： Hiroyuki Ohta ,  Kisho Ashida

IPC: G01B7/16 ,  G01L1/00 ,  G01L1/18 ,  G01M5/00 ,  H01L21/78

CPC classification number: G01B7/18 ,  G01L1/18 ,  G01M5/0083 ,  H01L21/78 ,  H01L2224/32 ,  H01L2924/10158

Abstract: Even when a strain sensor chip and an object to be measured are bonded to each other by using a metallic bonding material such as solder, the metallic bonding material shows the creep behavior when used under high temperature environment of, for example, 100° C. or higher, and therefore, the strain detected by the strain sensor chip is gradually reduced, and the strain is apparently reduced. In the strain sensor chip mounting structure which is one embodiment of the present application, a strain sensor chip is fixed onto a surface to be measured of the object to be measured via a metallic bonding material. And, the metallic bonding material is bonded to a metallic film that is formed on a side surface of the strain sensor chip. In this manner, temporal change in a measurement error can be suppressed.

公开(公告)号：US08278177B2

公开(公告)日：2012-10-02

申请号：US13240303

申请日：2011-09-22

Applicant: Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

Inventor： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

Abstract translation: 在沟槽中通过外延生长法形成第一p型SiGe混晶层，形成第二p型SiGe混晶层。 在第二SiGe混晶层上形成第三p型SiGe混晶层。 从沟槽底部开始的第一SiGe混合晶体层的最上表面的高度低于沟槽的深度，硅衬底的表面是标准的。 从沟槽底部开始的第二SiGe混合晶体层的最上表面的高度高于沟槽的深度，硅衬底的表面是标准的。 第一和第三SiGe混晶层中的Ge浓度低于第二SiGe混晶层中的Ge浓度。

公开(公告)号：US08183681B2

公开(公告)日：2012-05-22

申请号：US12493502

申请日：2009-06-29

Applicant: Shinji Hiramitsu ,  Hiroyuki Ohta ,  Koji Sasaki ,  Masato Nakamura ,  Osamu Ikeda ,  Satoshi Matsuyoshi

Inventor： Shinji Hiramitsu ,  Hiroyuki Ohta ,  Koji Sasaki ,  Masato Nakamura ,  Osamu Ikeda ,  Satoshi Matsuyoshi

IPC: H01L23/48

CPC classification number: H01L23/051 ,  H01L23/24 ,  H01L2224/33181

Abstract: A semiconductor device which includes a semiconductor chip; an electrically conductive base electrode bonded to the lower surface of the chip by a first bonding member; an electrically conductive lead electrode bonded to the upper surface of the chip by a second bonding member; and a first stress relief member for reducing stress developed in the first bonding member due to the difference in thermal expansion between the chip and the base electrode. Both the base electrode and the first stress relief member are in direct contact with the lower surface of the first bonding member. A protrusion is formed upstanding from the base electrode in direct contact with the first bonding member, and the first stress relief member surrounds a circumferential portion of the protrusion.

Abstract translation: 一种半导体器件，包括半导体芯片; 通过第一接合部件接合到所述芯片的下表面的导电基极; 通过第二接合部件将芯片的上表面接合的导电性引线电极; 以及由于芯片和基极之间的热膨胀差异，用于减小在第一接合部件中产生的应力的第一应力消除部件。 基极和第一应力消除构件都与第一接合构件的下表面直接接触。 从与第一接合构件直接接触的基极形成突起，并且第一应力消除构件围绕突起的周向部分。

公开(公告)号：US20110259112A1

公开(公告)日：2011-10-27

申请号：US13177185

申请日：2011-07-06

Applicant: Hiromi Shimazu ,  Hiroyuki Ohta ,  Yohei Tanno

Inventor： Hiromi Shimazu ,  Hiroyuki Ohta ,  Yohei Tanno

IPC: G01B7/16

CPC classification number: G01L1/2293 ,  G01B7/18 ,  G01L1/18

Abstract: A mechanical-quantity measuring device capable of measuring a strain component in a specific direction with high precision is provided.At least two or more pairs of bridge circuits are formed inside a semiconductor monocrystal substrate and a semiconductor chip, and one of these bridge circuits forms a n-type diffusion resistor in which a direction of a current flow and measuring variation of a resistor value are in parallel with a direction of the semiconductor monocryastal silicon substrate, and an another bridge circuit is composed of combination of p-type diffusion resistors in parallel with a direction.

Abstract translation: 提供能够高精度地测量特定方向的应变分量的机械量测量装置。 在半导体单晶基板和半导体芯片的内部形成有至少两对以上的桥式电路，并且这些桥式电路之一形成n型扩散电阻器，其中电流方向和电阻值的测量变化为 与半导体单晶硅基板的<100>方向并联，另一桥接电路由与<110>方向并联的p型扩散电阻器的组合构成。

公开(公告)号：US20100140711A1

公开(公告)日：2010-06-10

申请号：US12628364

申请日：2009-12-01

Applicant: Norio ISHITSUKA ,  Hiroyuki OHTA ,  Yasuhiro KIMURA ,  Natsuo YAMAGUCHI ,  Takashi TAKEUCHI ,  Shoji YOSHIDA

Inventor： Norio ISHITSUKA ,  Hiroyuki OHTA ,  Yasuhiro KIMURA ,  Natsuo YAMAGUCHI ,  Takashi TAKEUCHI ,  Shoji YOSHIDA

IPC: H01L27/12 ,  H01L21/86

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/6659

Abstract: Generation of dislocation and increase of diffusion resistance at edge portions of source/drain regions in a CMIS are prevented. When source/drain regions in a CMIS are formed, argon is implanted to a P-well layer as a dislocation-suppressing element and nitrogen is implanted to an N-well layer as a dislocation-suppressing element before an ion implantation of impurities to a silicon substrate. In this manner, by separately implanting dislocation-suppressing elements suitable for each of the P-well layer and the N-well layer as well as suppressing the generation of dislocation, increase of diffusion resistance can be suppressed, yield can be improved, and the reliability of devices can be increased.

Abstract translation: 防止在CMIS中的源极/漏极区域的边缘部分产生位错并增加扩散电阻。 当形成CMIS中的源极/漏极区时，将氩作为位错抑制元素注入到P阱层中，并且在离子将杂质离子注入到N阱之前将氮注入作为位错抑制元素的N阱层 硅衬底。 以这种方式，通过分别植入适合于P阱层和N阱层中的每一个的位错抑制元件以及抑制位错的产生，可以抑制扩散电阻的增加，可以提高产率，并且 可以提高设备的可靠性。

公开(公告)号：US07663187B2

公开(公告)日：2010-02-16

申请号：US11984738

申请日：2007-11-21

Applicant: Takashi Saiki ,  Hiroyuki Ohta ,  Hiroyuki Kanata

Inventor： Takashi Saiki ,  Hiroyuki Ohta ,  Hiroyuki Kanata

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.

Abstract translation: 通过栅极电极掩蔽下的离子注入形成延伸区域，然后在栅极电极和第一侧壁间隔物的掩蔽下注入在源极和漏极中包含的杂质上具有扩散抑制功能的物质，以便 在其表面层内形成半导体衬底并与第一侧壁间隔物对齐，从而形成非晶扩散抑制区域。

公开(公告)号：US07601996B2

公开(公告)日：2009-10-13

申请号：US11438684

申请日：2006-05-23

Applicant: Hiroyuki Ohta ,  Kenichi Okabe

Inventor： Hiroyuki Ohta ,  Kenichi Okabe

IPC: H01L29/76

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.

Abstract translation: 半导体器件包括布置在半导体衬底中的场效应晶体管，该晶体管具有栅电极，源/漏杂质扩散区和围绕源极/漏极杂质扩散区的碳层。 每个碳层设置在源极/漏极杂质扩散区域的相关联处，并且被定位成从远离栅电极的方向偏离源极/漏极延伸部的前边缘，并且作为轮廓围绕相关源 /漏杂质扩散区域。

公开(公告)号：US20090212437A1

公开(公告)日：2009-08-27

申请号：US12389071

申请日：2009-02-19

Applicant: Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

Inventor： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

IPC: H01L23/532

CPC classification number: H01L23/53238 ,  H01L23/3128 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.

Abstract translation: 在具有Low-k膜作为层间绝缘体的半导体器件中，防止了热循环试验中的层间绝缘体的剥离，从而提供高可靠性的半导体器件。 在具有这样的结构的半导体器件中，其中形成有由铜制成的主导电层的埋入布线和层叠埋入导线的帽绝缘体的层间绝缘体，所述盖绝缘体具有较高的杨氏模量并且通过其接触 形成具有相对低的杨氏模量的由Low-k膜制成的层间绝缘体的上表面，以便不设置在半导体器件的边缘部分中。

公开(公告)号：US20080203475A1

公开(公告)日：2008-08-28

申请号：US11984738

申请日：2007-11-21

Applicant: Takashi Saiki ,  Hiroyuki Ohta ,  Hiroyuki Kanata

Inventor： Takashi Saiki ,  Hiroyuki Ohta ,  Hiroyuki Kanata

IPC: H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.

公开(公告)号：US07321151B2

公开(公告)日：2008-01-22

申请号：US10800749

申请日：2004-03-16

Applicant: Takashi Saiki ,  Hiroyuki Ohta ,  Hiroyuki Kanata

Inventor： Takashi Saiki ,  Hiroyuki Ohta ,  Hiroyuki Kanata

IPC: H01L29/76

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.