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1.发明授权Timing adjustment circuit for a memory interface and method of adjusting timing for memory interface 有权用于存储器接口的定时调整电路和调整存储器接口时序的方法公开(公告)号：US08582376B2
公开(公告)日：2013-11-12
申请号：US13236007
申请日：2011-09-19
IPC分类号： G11C7/00
CPC分类号： G11C29/028 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C29/022 , G11C29/023
摘要： According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.
摘要翻译： 根据一个实施例，提出了一种用于存储器接口的定时调整电路。 该电路设置有门电路，原始门信号发生电路，高阻抗防止单元，阻抗控制单元和门平衡电路。 门电路执行从存储器输出的数据选通信号的门控。 原始门信号发生电路根据读等待时间和突发长度的信息产生原始门信号。 高阻抗防止单元，用于防止数据选通信号处于高阻抗状态。 阻抗控制单元控制高阻抗防止单元的操作的执行和释放。 门平衡电路基于原始门信号和数据选通信号，向门电路输出定时调整后的门信号。
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2.发明申请TIMING ADJUSTMENT CIRCUIT FOR A MEMORY INTERFACE AND METHOD OF ADJUSTING TIMING FOR MEMORY INTERFACE 有权用于存储器接口的时序调整电路和用于记忆接口调整时序的方法公开(公告)号：US20120188833A1
公开(公告)日：2012-07-26
申请号：US13236007
申请日：2011-09-19
IPC分类号： G11C8/18
CPC分类号： G11C29/028 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C29/022 , G11C29/023
摘要： According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.
摘要翻译： 根据一个实施例，提出了一种用于存储器接口的定时调整电路。 该电路设置有门电路，原始门信号发生电路，高阻抗防止单元，阻抗控制单元和门平衡电路。 门电路执行从存储器输出的数据选通信号的门控。 原始门信号发生电路根据读等待时间和突发长度的信息产生原始门信号。 高阻抗防止单元，用于防止数据选通信号处于高阻抗状态。 阻抗控制单元控制高阻抗防止单元的操作的执行和释放。 门平衡电路基于原始门信号和数据选通信号，向门电路输出定时调整后的门信号。
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