公开(公告)号：US4110706A

公开(公告)日：1978-08-29

申请号：US730292

申请日：1976-10-06

申请人： Youichi Matsumoto ,  Yoshimi Tagashira ,  Seijiro Yokoyama

发明人： Youichi Matsumoto ,  Yoshimi Tagashira ,  Seijiro Yokoyama

IPC分类号： H04L27/227 ,  H03C3/00

CPC分类号： H04L27/2277

摘要： A synchronizing circuit for reproducing a synchronizing carrier wave from a received N-phase (N=2.sup.n, n being a positive real integer where n .gtoreq.1) PSK modulated carrier wave and employing a code converter circuit for adjusting the phase states of the received modulated carrier after demodulation thereof in order to enable the modulator to generate signals of the proper phase relation relative to an output carrier wave of a voltage controlled oscillator, which phase relationship is detected by a phase detector.The code converter may be a logic gating circuit having control inputs for changing the output levels or a plurality of branching circuit pairs for each input each pair having a true and complement branch, and switch means for selectively coupling one of the branches to an output associated with each pair of branch circuits.

摘要翻译： 一种同步电路，用于从接收的N相（N = 2n，n为正实数整数，其中n> / = 1）PSK调制载波再现同步载波，并采用代码转换器电路来调整相位状态 在解调之后接收调制载波，以使得调制器能够产生相对于压控振荡器的输出载波的适当相位关系的信号，该相位关系由相位检测器检测。

公开(公告)号：US4285062A

公开(公告)日：1981-08-18

申请号：US79725

申请日：1979-09-28

申请人： Yasuharu Yoshida ,  Yoshimi Tagashira ,  Seijiro Yokoyama

发明人： Yasuharu Yoshida ,  Yoshimi Tagashira ,  Seijiro Yokoyama

IPC分类号： H04J9/00 ,  H04L27/02 ,  H04L27/18 ,  H04L27/22 ,  H04L27/34 ,  H04L27/36 ,  H04L27/38 ,  H04L3/00

CPC分类号： H04L27/02 ,  H04L27/362 ,  H04L27/3872

摘要： A digital multi-level multi-phase modulation system utilizes quaternary differential encoding and decoding of only the first two of N digital signal trains. A decision circuit is used to examine the frame pulses in one of the first two signal trains and in at least one of the remaining signal trains and generates output signals which can be used in a gate circuit to resolve the phase-lock ambiguity of the recovered carrier and thereby reproduce the original N signal trains.

摘要翻译： 数字多电平多相调制系统仅使用N个数字信号序列中的前两个的四进制差分编码和解码。 使用判定电路来检查前两个信号列之一和剩余信号列中的至少一个中的帧脉冲，并且产生输出信号，其可以在门电路中使用以解决所恢复的相位锁定模糊度 从而再现原始的N信号列车。

公开(公告)号：US3978406A

公开(公告)日：1976-08-31

申请号：US603901

申请日：1975-08-11

申请人： Youichi Matsumoto ,  Seijiro Yokoyama ,  Tadao Shimamura

发明人： Youichi Matsumoto ,  Seijiro Yokoyama ,  Tadao Shimamura

IPC分类号： H04L27/00 ,  H04L1/00 ,  H04L27/18 ,  H04L27/20 ,  H04L27/227 ,  H04L1/10

CPC分类号： H04L1/0061 ,  H04L27/2046 ,  H04L27/2277

摘要： A code error detection system in a digital phase modulation communication system comprises on the transmitter side a first code train generator for generating a pseudo-random code train and a second code train generator for generating codes which are complementary to each other at n-bit intervals. A 4-phase phase modulator is driven by another code representative of the exclusive OR function of the pseudo-random and complementary codes.