摘要:
Nonvolatile memory devices include a plurality of nonvolatile memory cells and a write circuit that is operable to write data to the nonvolatile memory cells over a plurality of consecutive division write periods by generating a plurality of write pulses whose peaks do not coincide with one another to the nonvolatile memory cells.
摘要:
Nonvolatile memory devices include a plurality of nonvolatile memory cells and a write circuit that is operable to write data to the nonvolatile memory cells over a plurality of consecutive division write periods by generating a plurality of write pulses whose peaks do not coincide with one another to the nonvolatile memory cells.
摘要:
Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.
摘要:
Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.
摘要:
Integrated circuit devices include a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates an output signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative. Because the comparator is responsive to the relative difference between the voltage levels of the first and second differential input signals and not the absolute magnitudes of the voltage levels, fuse remnants that may exist after the fuse programmable input circuit has been programmed (i.e., one or more fuses have been cut) typically do not affect the output signal.