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    Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same
    2.
    发明授权
    Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same 有权
    具有可变电阻存储单元的非易失性存储器件及其编程方法

    公开(公告)号：US08199603B2

    公开(公告)日：2012-06-12

    申请号：US12498549

    申请日：2009-07-07

    申请人： Won-Ryul Chung ,  Byung-Gil Choi ,  In-Cheol Shin ,  Ki-Won Lim

    发明人： Won-Ryul Chung ,  Byung-Gil Choi ,  In-Cheol Shin ,  Ki-Won Lim

    IPC分类号： G11C8/00

    CPC分类号： G11C13/0038 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

    摘要： Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.

    摘要翻译： 非易失性存储器件包括可变电阻存储器单元阵列和电耦合到阵列的写入驱动器。 写入驱动器被配置为在用于编程所述阵列中的可变电阻存储器单元的操作期间，在具有至少两个不相等的位线电压的阶梯序列的驱动可变电阻存储器单元阵列中的位线。 至少两个不等位线电压的阶梯级序列包括第一步骤的预充电电压（例如Vcc-Vth）和跟随第一步骤的第二步骤的较高升压电压（例如，Vpp-Vth）。

    Nonvolatile memory device using a variable resistive element and associated operating method
    5.
    发明授权
    Nonvolatile memory device using a variable resistive element and associated operating method 有权
    使用可变电阻元件和相关操作方法的非易失性存储器件

    公开(公告)号：US07817479B2

    公开(公告)日：2010-10-19

    申请号：US12136822

    申请日：2008-06-11

    申请人： Yu-Hwan Ro ,  Byung-Gil Choi ,  In-Cheol Shin

    发明人： Yu-Hwan Ro ,  Byung-Gil Choi ,  In-Cheol Shin

    IPC分类号： G11C16/04

    CPC分类号： G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

    摘要： A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.

    摘要翻译： 使用提供在存储器件外部的电压和在器件内产生的电压而不是仅使用在器件内产生的电压作为驱动电压的非易失性存储器件避免了当出现瞬时显着电压下降时存储器件的故障。 非易失性存储器件包括多个非易失性存储器单元，耦合到多个非易失性存储器单元的至少一部分的位线，耦合到位线的列选择晶体管和驱动电路。 驱动电路耦合到列选择晶体管的栅极，并且被配置为使用其中第二电压高于第一电压的第一电压和第二电压向栅极提供电荷。

    Resistive memory employing different pulse width signals for reading different memory cells
    6.
    发明授权
    Resistive memory employing different pulse width signals for reading different memory cells 有权
    采用不同脉冲宽度信号读取不同存储单元的电阻式存储器

    公开(公告)号：US08369136B2

    公开(公告)日：2013-02-05

    申请号：US12662985

    申请日：2010-05-14

    申请人： Byung-Gil Choi

    发明人： Byung-Gil Choi

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004 ,  G11C2013/0052 ,  G11C2213/72

    摘要： A semiconductor memory includes a memory cell array including a plurality of memory cells arranged in rows and columns, a plurality of bit lines, each bit line connected to a corresponding column of the memory cells; a column selection circuit configured to select at least one bit line in response to a column select signal; and a read circuit configured to precharge the selected bit line in response to a precharge signal, to apply a read bias to the precharged bit line in response to a read bias provision signal, and to read data from the memory cells. A resistance level of each of the memory cells varies according to data stored therein, and the read circuit reads data from a first memory cell of the plurality of memory cells in response to the precharge signal having a first pulse width and reads data from a second memory cell of the plurality of memory cells in response to the precharge signal having a second pulse width.

    摘要翻译： 半导体存储器包括存储单元阵列，其包括以行和列排列的多个存储单元，多个位线，每个位线连接到存储单元的相应列; 列选择电路，被配置为响应于列选择信号选择至少一个位线; 以及读取电路，其被配置为响应于预充电信号对所选择的位线进行预充电，以响应于读取偏置提供信号将读取偏压施加到预充电位线，并从存储器单元读取数据。 每个存储单元的电阻电平根据存储在其中的数据而变化，并且读取电路响应于具有第一脉冲宽度的预充电信号从多个存储单元的第一存储单元读取数据，并从第二 响应于预充电信号具有第二脉冲宽度的多个存储单元的存储单元。

    Nonvolatile memory devices using variable resistive elements
    7.
    发明授权
    Nonvolatile memory devices using variable resistive elements 有权
    使用可变电阻元件的非易失性存储器件

    公开(公告)号：US08184468B2

    公开(公告)日：2012-05-22

    申请号：US12453529

    申请日：2009-05-14

    申请人： Ki-Sung Kim ,  Byung-Gil Choi ,  Young-Ran Kim ,  Jong-Chul Park

    发明人： Ki-Sung Kim ,  Byung-Gil Choi ,  Young-Ran Kim ,  Jong-Chul Park

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0023 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/72

    摘要： A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory cells having variable resistance levels depending on data stored. Word lines may be coupled with each column of the nonvolatile memory cells. Local bit lines may be coupled with each row of the nonvolatile memory cells. Global bit lines may be selectively coupled with the multiple local bit lines.

    摘要翻译： 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件可以包括存储单元阵列，其包括具有取决于存储的数据的可变电阻等级的多个非易失性存储单元的阵列。 字线可以与非易失性存储单元的每一列耦合。 局部位线可以与非易失性存储器单元的每一行耦合。 全局位线可以选择性地与多个局部位线耦合。

    Resistance variable memory device reducing word line voltage
    8.
    发明授权
    Resistance variable memory device reducing word line voltage 有权
    电阻可变存储器件减少字线电压

    公开(公告)号：US07830699B2

    公开(公告)日：2010-11-09

    申请号：US12245929

    申请日：2008-10-06

    申请人： Byung-Gil Choi ,  Du-Eung Kim

    发明人： Byung-Gil Choi ,  Du-Eung Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

    摘要： A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block.

    摘要翻译： 电阻可变存储器件包括存储单元阵列，读出放大器电路和列选择电路。 存储单元阵列包括多个块单元和多个字线驱动器，其中每个块单元连接在相邻字线驱动器之间并且包括多个存储块。 读出放大器电路包括多个读出放大器单元，其中每个读出放大器单元向对应的块单元提供读取电流并且包括多个读出放大器。 列选择电路连接在存储单元阵列和读出放大器电路之间，并响应于列选择信号选择多个存储块中的至少一个，以将读出的电流从读出放大器电路施加到所选存储块。

    Nonvolatile Memory Device Using Variable Resistive Element
    9.
    发明申请
    Nonvolatile Memory Device Using Variable Resistive Element 有权
    使用可变电阻元件的非易失性存储器件

    公开(公告)号：US20100142254A1

    公开(公告)日：2010-06-10

    申请号：US12630484

    申请日：2009-12-03

    申请人： Byung-Gil Choi ,  Joon-Yong Choi

    发明人： Byung-Gil Choi ,  Joon-Yong Choi

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C8/10 ,  G11C8/14 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2213/72

    摘要： A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device includes first and second nonvolatile memory cells. Word lines are coupled to the first and second nonvolatile memory cells. First and second bit lines are coupled to the first and second nonvolatile memory cells, respectively. A read circuit reads resistance levels of the first and second nonvolatile memory cells by providing first and second read bias currents of different levels to the first and second bit lines, respectively.

    摘要翻译： 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件包括第一和第二非易失性存储单元。 字线耦合到第一和第二非易失性存储单元。 第一和第二位线分别耦合到第一和第二非易失性存储器单元。 读取电路通过分别向第一和第二位线提供不同电平的第一和第二读取偏置电流来读取第一和第二非易失性存储器单元的电阻电平。

    NONVOLATILE MEMORY USING RESISTANCE MATERIAL
    10.
    发明申请
    NONVOLATILE MEMORY USING RESISTANCE MATERIAL 有权
    使用电阻材料的非易失性存储器

    公开(公告)号：US20090122600A1

    公开(公告)日：2009-05-14

    申请号：US12243578

    申请日：2008-10-01

    申请人： Joon-Yong Choi ,  Byung-Gil Choi

    发明人： Joon-Yong Choi ,  Byung-Gil Choi

    IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C13/0069 ,  G11C7/18 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0078

    摘要： A nonvolatile memory using a resistance material includes first and second memory-cell blocks having different block address information and each including a plurality of nonvolatile memory cells; a global bitline common to the first and second memory-cell blocks; first and second local bitlines corresponding to the first and second memory-cell blocks, respectively, and coupled to each other; and a common bitline selection circuit interposed between the first and second memory-cell blocks and coupled between the first and second local bitlines and the global bitline.

    摘要翻译： 使用电阻材料的非易失性存储器包括具有不同块地址信息并且各自包括多个非易失性存储单元的第一和第二存储单元块; 第一和第二存储单元块共同的全局位线; 分别对应于第一和第二存储单元块的第一和第二局部位线并彼此耦合; 以及插入在第一和第二存储单元块之间并耦合在第一和第二本地位线与全局位线之间的公共位线选择电路。