公开(公告)号：US20080105899A1

公开(公告)日：2008-05-08

申请号：US11858288

申请日：2007-09-20

申请人： Young-pil KIM ,  Jin-bum KIM ,  Jun-ho LEE ,  Jung-yun WON ,  In-sun JUNG

发明人： Young-pil KIM ,  Jin-bum KIM ,  Jun-ho LEE ,  Jung-yun WON ,  In-sun JUNG

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/78

摘要： A fabrication method and a related semiconductor device are disclosed. The method includes; forming a gate structure on a semiconductor substrate, the gate structure comprising a stacked combination a gate dielectric pattern, a gate, a capping layer pattern and an epitaxial blocking layer pattern, forming sidewall spacers on the gate structure covering at least sidewall portions of the gate dielectric pattern, the gate, and the capping layer pattern, wherein the epitaxial blocking layer pattern is exposed on a top surface of the gate structure, forming an elevated epitaxial layer on the semiconductor substrate outside the gate structure using a selective epitaxial growth process, and forming elevated source/drain regions by applying an ion implantation process to the semiconductor substrate following formation of the elevated epitaxial layer, wherein the epitaxial blocking layer is a nitrogen enhanced layer relative to the capping layer pattern.

摘要翻译： 公开了一种制造方法和相关的半导体器件。 该方法包括： 在半导体衬底上形成栅极结构，所述栅极结构包括层叠组合栅极电介质图案，栅极，覆盖层图案和外延阻挡层图案，在所述栅极结构上形成至少覆盖所述栅极的侧壁部分的侧壁间隔物 电介质图案，栅极和覆盖层图案，其中外延阻挡层图案暴露在栅极结构的顶表面上，使用选择性外延生长工艺在栅极结构外部的半导体衬底上形成升高的外延层，以及 通过在形成升高的外延层之后对半导体衬底施加离子注入工艺来形成升高的源/漏区，其中外延阻挡层相对于覆盖层图案是氮增强层。

公开(公告)号：US20080105930A1

公开(公告)日：2008-05-08

申请号：US11855529

申请日：2007-09-14

申请人： Jin-bum KIM ,  Young-pil KIM ,  Si-young CHOI ,  Byeong-chan LEE ,  Jong-wook LEE

发明人： Jin-bum KIM ,  Young-pil KIM ,  Si-young CHOI ,  Byeong-chan LEE ,  Jong-wook LEE

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823418 ,  H01L21/823456 ,  H01L27/105 ,  H01L27/1052

摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.

摘要翻译： 本发明的实施例提供一种半导体集成电路器件及其制造方法。 半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由 隔离区。 半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层 所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

公开(公告)号：US20100240197A1

公开(公告)日：2010-09-23

申请号：US12793809

申请日：2010-06-04

申请人： Jin-bum KIM ,  Young-pil KIM ,  Si-young CHOI ,  Byeong-chan LEE ,  Jong-wook LEE

发明人： Jin-bum KIM ,  Young-pil KIM ,  Si-young CHOI ,  Byeong-chan LEE ,  Jong-wook LEE

IPC分类号： H01L21/20

CPC分类号： H01L21/823418 ,  H01L21/823456 ,  H01L27/105 ,  H01L27/1052

摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.

摘要翻译： 本发明的实施例提供一种半导体集成电路器件及其制造方法。 半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由 隔离区。 半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层 所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

公开(公告)号：US20160087053A1

公开(公告)日：2016-03-24

申请号：US14861794

申请日：2015-09-22

申请人： Jin-bum KIM ,  Chul-sung KIM ,  Deok-han BAE ,  Bon-young KOO

发明人： Jin-bum KIM ,  Chul-sung KIM ,  Deok-han BAE ,  Bon-young KOO

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/41783 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

摘要翻译： 半导体器件可以包括具有NMOS区域和PMOS区域的基板，并且具有突起图案; 第一和第二栅极结构分别形成在衬底的NMOS区域和PMOS区域上，与突起图案交叉并且沿着平行于衬底的上表面的第一方向延伸; 形成在第一和第二栅极结构的两侧上的第一和第二源极/漏极区域; 以及分别形成在第一和第二源极/漏极区域上的第一和第二接触插塞，其中第一接触插塞和第二接触插塞是不对称的。 还提供了制造方法。