公开(公告)号：US6001660A

公开(公告)日：1999-12-14

申请号：US969672

申请日：1997-11-13

申请人： Young-soh Park ,  Sang-in Lee ,  Cheol-seong Hwang ,  Doo-sup Hwang ,  Hag-Ju Cho

发明人： Young-soh Park ,  Sang-in Lee ,  Cheol-seong Hwang ,  Doo-sup Hwang ,  Hag-Ju Cho

IPC分类号： C23C14/14 ,  C23C14/58 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01G7/06

CPC分类号： H01L28/60 ,  H01L21/76882

摘要： Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12. According to one embodiment of the present invention, the step of patterning the electrically insulating layer comprises patterning the electrically insulating layer to define a contact hole therein that exposes the face of the semiconductor substrate. The step of forming a barrier metal layer also preferably comprises depositing a conformal barrier metal layer on sidewalls of the contact hole and on the exposed face of the substrate. The barrier metal layer may be selected from the group consisting of TiN, CoSi, TaSiN, TiSiN, TaSi, TiSi, Ta and TaN.

摘要翻译： 形成集成电路电容器的方法包括以下步骤：在半导体衬底的表面上形成电绝缘层，然后对电绝缘层进行构图以在其中限定接触孔。 然后在接触孔的至少一部分中形成阻挡金属层。 然后在阻挡金属层上形成下电极金属层，然后通过在氮气环境中在大于约650℃的温度下回流下电极金属层来平坦化，以限定较低的电容器电极。 然后在下部电容器电极上形成具有高介电常数的材料层。 然后在电介质层上形成上电容器电极，与下电容器电极相对。 介电层可以包括Ba（Sr，Ti）O3，Pb（Zr，Ti）O3，Ta2O5，SiO2，SiN3，SrTiO3，PZT，SrBi2Ta2O9，（Pb，La）（Zr，Ti）O3和Bi4Ti3O12。 根据本发明的一个实施例，图案化电绝缘层的步骤包括图案化电绝缘层以限定其中露出半导体衬底的表面的接触孔。 形成阻挡金属层的步骤还优选包括在接触孔的侧壁上和基底的暴露面上沉积保形阻挡金属层。 阻挡金属层可以选自TiN，CoSi，TaSiN，TiSiN，TaSi，TiSi，Ta和TaN。

公开(公告)号：US5776638A

公开(公告)日：1998-07-07

申请号：US609124

申请日：1996-02-29

申请人： Young-soh Park ,  Joo-young Lee ,  Young-hun Yu

发明人： Young-soh Park ,  Joo-young Lee ,  Young-hun Yu

IPC分类号： G03F1/28 ,  G03F1/68 ,  G03F7/20 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/26 ,  G03F7/70191

摘要： A method of projection exposure utilizing a mask including a step of exposing an object by utilizing a transparent mask substrate of which the upper surface is slanted at a predetermined angle from a direction perpendicular to the light path and an opaque film pattern is formed at regular intervals on a lower surface of the mask substrate so that the phase difference between adjacent mask patterns occurs due to the slanted mask substrate, thereby reducing the minimum pitch available for pattern formation without a shorter-wavelength light source and without increasing NA by reducing the frequency difference .delta.v to the pitch d of the mask in a given wavelength of a light source and NA.

摘要翻译： 一种利用掩模的投影曝光方法，包括通过利用上表面以垂直于光路的方向以预定角度倾斜的透明掩模基板和以不规则的间隔形成不透明胶片图案来曝光物体的步骤 在掩模基板的下表面上，由于倾斜的掩模基板而产生相邻掩模图案之间的相位差，从而降低了可用于图案形成的最小间距，而不需要较短波长的光源，并且通过降低频率差异而不增加NA delta v为光源的给定波长中的掩模的间距d和NA。