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公开(公告)号：US4978627A
公开(公告)日：1990-12-18
申请号：US443886
申请日：1989-11-30
IPC分类号： H01L21/336
CPC分类号： H01L29/6659
摘要： A process for fabricating field effect transistors with lightly doped drain (LDD) regions having a selected width includes a method of optically detecting the width of spacers used to mask the LDD regions during the source and drain implant and a method of electrically determining (confirming) the width of the LDD regions. In the optical method, reference structures are formed concurrently with the fabrication of the gates for FETs, a spacer material is formed on the substrate, the gates and the reference structures, the spacer material is etched away and the width of the spacers is optically detected by aligning the edges of spacers extending from two reference structures separated by a known distance. In the electrical method, the width is determined by defining a test area with known dimension, forming both N.sup.+ and N.sup.- regions in the test area, measuring the resistance across the test area, calculating the resistance of the N.sup.+ and N.sup.- regions, and calculating the width of the N.sup.- region from the resistance of the N.sup.- region. The electrically determined width is compared with the desired LDD region width, and the difference between the electrically determined width and the desired width is used to adjust the distance between the reference structures for a subsequent processing run.
摘要翻译： 用于制造具有选定宽度的具有轻掺杂漏极（LDD）区域的场效应晶体管的方法包括在源极和漏极注入期间光学检测用于掩蔽LDD区的间隔物的宽度的方法，以及电确定（确认） LDD区域的宽度。 在光学方法中，与FET的栅极的制造同时形成参考结构，在衬底，栅极和参考结构上形成间隔物材料，蚀刻掉间隔物材料并且光学地检测间隔物的宽度 通过对准由已知距离分开的两个参考结构延伸的间隔件的边缘。 在电气方法中，通过限定具有已知尺寸的测试区域来确定宽度，在测试区域中形成N +和N-区域，测量测试区域上的电阻，计算N +和N-区域的电阻，以及 从N区的电阻计算N-区的宽度。 将电确定的宽度与期望的LDD区域宽度进行比较，并且使用电确定的宽度和期望宽度之间的差来调整用于后续处理运行的参考结构之间的距离。
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2.发明授权Method of fabricating field effect transistors having lightly doped drain regions 失效制造具有轻掺杂漏极区域的场效应晶体管的方法
公开(公告)号：US5200351A
公开(公告)日：1993-04-06
申请号：US837536
申请日：1992-02-14
IPC分类号： H01L21/311 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/31111 , H01L21/31116
摘要： A method of forming and removing spacers used to mask lightly doped drain (LDD) regions in the formation of a field effect transistor (FET) involves depositing a thin silicon nitride (Si.sub.3 N.sub.4) layer over the active region of a substrate, a gate structure formed on the active region, and over the field oxide regions. A silicon oxide (SiO.sub.2) film is provided over the nitride and then etched to form LDD spacers at the ends of the gate. The etchant used to etch the oxide layer selectively etches oxide at least 20 times faster than nitride. The nitride layer protects the field oxide regions from etching, thereby preventing oxide loss. The spacers are used to mask regions in the substrate during the implantation of source and drain regions, and the masked regions become the LDD regions. After implanting the source and drain regions, the nitride layer may be removed with a wet etchant which selectively etches nitride. The LDD spacers will be lifted off by the removal of the nitride layer or the spacer may be removed with a wet etchant which selectively etches silicon oxide followed by a nitride wet etchant which selectively etches nitride.
摘要翻译： 在形成场效应晶体管（FET）的过程中，形成和去除用于掩蔽轻掺杂漏极（LDD）区的间隔物的方法包括在衬底的有源区上沉积薄的氮化硅（Si 3 N 4）层，形成栅极结构 在活性区域上和场氧化物区域上。 在氮化物之上提供氧化硅（SiO 2）膜，然后蚀刻以在栅极的端部形成LDD间隔物。 用于蚀刻氧化物层的蚀刻剂选择性地蚀刻氧化物比氮化物快至少20倍。 氮化物层保护场氧化物区域免受蚀刻，从而防止氧化物损失。 在源极和漏极区域的注入期间，间隔物用于掩蔽衬底中的区域，并且掩蔽区域成为LDD区域。 在注入源极区和漏极区之后，可以用选择性蚀刻氮化物的湿蚀刻剂去除氮化物层。 通过去除氮化物层将剥离LDD间隔物，或者可以用选择性地蚀刻二氧化硅，然后选择性蚀刻氮化物的氮化物湿蚀刻剂的湿蚀刻剂除去间隔物。
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3.发明授权
公开(公告)号：US5013675A
公开(公告)日：1991-05-07
申请号：US355634
申请日：1989-05-23
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/7833
摘要： A method of forming and removing spacers used to mask lightly doped drain (LDD) regions in the formation of a field effect transistor (FET) involves depositing a thin oxide layer over the active region of a substrate and a gate structure formed on the active region. A polysilicon film is provided over the oxide and then doped using a POCl.sub.3 dopant. The polysilicon layer is then etched to form spacers at the ends of the gate and the spacers are used to mask lightly doped drain regions in the substrate during the implantation of source and drain regions. After the implant to form the source and drain regions, the device is subjected to a rapid thermal annealing for approximately 20-60 seconds at approximately 900.degree. C. in an inert atmosphere to cure any damage to the oxide layer which occurs during the source/drain implant. Curing the oxide layer reduces the etch rate of the oxide layer for an etchant which is designed to selectively etch the polysilicon spacers faster than it etches the oxide layer. The POCl.sub.3 doping of the polysilicon layer increases the etch rate of the polysilicon, thus enhancing the selectivity of the etching of the polysilicon versus the oxide layer.
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4.发明授权
公开(公告)号：US5010029A
公开(公告)日：1991-04-23
申请号：US313984
申请日：1989-02-22
IPC分类号： H01L21/336 , H01L21/66 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/78
摘要： A process for fabricating field effect transistors with lightly doped drain (LDD) regions having a selected width includes a method of optically detecting the width of spacers used to mask the LDD regions during the source and drain implant and a method of electrically determining (confirming) the width of the LDD regions. In the optical method, reference structures are formed concurrently with the fabrication of the gates for FETs, a spacer material is formed on the substrate, the gates and the reference structures, the spacer material is etched away and the width of the spacers is optically detected by aligning the edges of spacers extending from two reference structures separated by a known distance. In the electrical method, the width is determined by defining a test area with known dimension, forming both N.sup.+ and N.sup.- regions in the test area, measuring the resistance across the test area, calculating the resistance of the N.sup.+ and N.sup.- regions, and calculating the width of the N.sup.- region from the resistance of the N.sup.- region.
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