公开(公告)号：US07192845B2

公开(公告)日：2007-03-20

申请号：US10864562

申请日：2004-06-08

Applicant: Yu Lin Yen ,  Ching-Yu Chang

Inventor： Yu Lin Yen ,  Ching-Yu Chang

IPC: H01L21/76 ,  H01L21/78 ,  H01L21/46 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on the first layer. Portions of the second and/or third layer are selectively removed from regions in and around the first overlay mark. A second overlay mark is formed and aligned to the first overlay mark. The alignment between the second overlay mark and first overlay mark may be measured with an attenuated error due to reflection and refraction or due to an edge profile shift of the first overlay mark.

Abstract translation: 一种集成电路，其中后续层之间的对准测量对应力诱导偏移具有较小的敏感性。 该结构的第一层具有第一覆盖标记。 在对准结构中和第一层上形成第二层和/或第三层。 第二层和/或第三层的部分从第一重叠标记中和周围的区域选择性地去除。 形成第二重叠标记并与第一覆盖标记对准。 可以由于反射和折射或由于第一重叠标记的边缘轮廓偏移而具有衰减误差来测量第二覆盖标记和第一覆盖标记之间的对准。