公开(公告)号：US07728915B2

公开(公告)日：2010-06-01

申请号：US11802347

申请日：2007-05-22

Applicant: Yu-Hsin Ting ,  Ya-Chun Lee

Inventor： Yu-Hsin Ting ,  Ya-Chun Lee

IPC: G02F1/1343

CPC classification number: G02F1/136213 ,  G02F1/136227

Abstract: A pixel structure of the present invention includes two metal plates and a transistor. The metal plates are electrically connected together. The gate of the transistor receives a scan signal. The drain of the transistor receives a data signal. The source of the transistor includes two extending portions. A store capacitor is formed between the two extending portions and the two metal plates. The two extending portions are plate structures.

Abstract translation: 本发明的像素结构包括两个金属板和一个晶体管。 金属板电连接在一起。 晶体管的栅极接收扫描信号。 晶体管的漏极接收数据信号。 晶体管的源极包括两个延伸部分。 在两个延伸部分和两个金属板之间形成一个储存电容器。 两个延伸部分是板结构。

公开(公告)号：US20080100761A1

公开(公告)日：2008-05-01

申请号：US11802347

申请日：2007-05-22

Applicant: Yu-Hsin Ting ,  Ya-Chun Lee

Inventor： Yu-Hsin Ting ,  Ya-Chun Lee

IPC: G02F1/1343

CPC classification number: G02F1/136213 ,  G02F1/136227

Abstract: A pixel structure of the present invention includes two metal plates and a transistor. The metal plates are electrically connected together. The gate of the transistor receives a scan signal. The drain of the transistor receives a data signal. The source of the transistor includes two extending portions. A store capacitor is formed between the two extending portions and the two metal plates. The two extending portions are plate structures.

Abstract translation: 本发明的像素结构包括两个金属板和一个晶体管。 金属板电连接在一起。 晶体管的栅极接收扫描信号。 晶体管的漏极接收数据信号。 晶体管的源极包括两个延伸部分。 在两个延伸部分和两个金属板之间形成一个储存电容器。 两个延伸部分是板结构。

公开(公告)号：US08766899B2

公开(公告)日：2014-07-01

申请号：US13087328

申请日：2011-04-14

Applicant: Wei-Chun Hsu ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Pei-Hua Chen

Inventor： Wei-Chun Hsu ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Pei-Hua Chen

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2320/0214

Abstract: An active liquid crystal display panel includes a pixel array, a gate driving circuit, a data driving circuit, and an analog buffer. The gate driving circuit is used for driving M first scan lines where M is a natural number. The analog buffer is coupled to the gate driving circuit and includes M buffer circuits and a regulator. Each buffer circuit drives a corresponding second scan line according to an output signal of a corresponding first scan line of the M first scan lines, and the regulator is used for maintaining at least one reference voltage supplied to the M buffer circuits.

Abstract translation: 有源液晶显示面板包括像素阵列，栅极驱动电路，数据驱动电路和模拟缓冲器。 栅极驱动电路用于驱动M是自然数的M个第一扫描线。 模拟缓冲器耦合到栅极驱动电路，并包括M个缓冲电路和调节器。 每个缓冲电路根据M个第一扫描线的对应的第一扫描线的输出信号驱动相应的第二扫描线，并且调节器用于保持提供给M个缓冲电路的至少一个参考电压。

公开(公告)号：US20130141315A1

公开(公告)日：2013-06-06

申请号：US13661239

申请日：2012-10-26

Applicant: Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

Inventor： Pei-Hua Chen ,  Yu-Hsin Ting ,  Chung-Lin Fu ,  Tsao-Wen Lu ,  Nan-Ying Lin ,  Wei-Chun Hsu

IPC: G11C19/00 ,  G09G3/20

CPC classification number: G11C19/28 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/38 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/184

Abstract: A shift register includes shift register units, in which at least one shift register unit is coupled to a forestage shift register unit and a post-stage shift register unit, where the at least one shift register unit includes a signal input circuit, a signal output circuit, a pull down circuit and a switching circuit. The signal input circuit electrically coupled to the forestage shift register unit can receive a logic signal from the forestage shift register. The signal output circuit is electrically coupled to the signal input circuit via a control signal terminal and is electrically coupled to the post-stage shift register unit. The signal output to circuit can receive a first clock signal. The pull down circuit is electrically coupled to or electrically isolated from the control signal terminal through the switching circuit.

Abstract translation: 移位寄存器包括移位寄存器单元，其中至少一个移位寄存器单元耦合到林格移位寄存器单元和后级移位寄存器单元，其中至少一个移位寄存器单元包括信号输入电路，信号输出 电路，下拉电路和开关电路。 电连接到林间移位寄存器单元的信号输入电路可以从林格移位寄存器接收逻辑信号。 信号输出电路经由控制信号端子电耦合到信号输入电路，并且电耦合到后级移位寄存器单元。 输出到电路的信号可以接收第一个时钟信号。 下拉电路通过开关电路与控制信号端子电耦合或电隔离。

公开(公告)号：US07830352B2

公开(公告)日：2010-11-09

申请号：US11332922

申请日：2006-01-17

Applicant: Xuan-Fang Shi ,  Yu-Hsin Ting ,  Jian-Shen Yu

Inventor： Xuan-Fang Shi ,  Yu-Hsin Ting ,  Jian-Shen Yu

IPC: G09G3/36 ,  G11C19/00

CPC classification number: G09G3/3688 ,  G09G3/3648 ,  G09G2310/0248

Abstract: A driving circuit. The driving circuit includes a plurality of scan shift register cells, a pair of complementary clock signal lines, and a horizontal start signal generator. Each scan shift register cell comprises a bidirectional circuit, a shift register coupled to the bidirectional circuit, a transmission gate coupled to the shift register, and a data line coupled to the transmission gate. The complementary clock signal lines are coupled to the shift registers. The horizontal start signal generator provides a horizontal start signal to the bidirectional circuits in the first and a subsequent scan shift register cells. The shift register in each scan shift register cell provides an output signal to the bidirectional circuit in the next scan shift register cell. The bidirectional circuit in each scan shift register cell also receives the output signal from the shift register in the next scan shift register cell.

Abstract translation: 驱动电路。 驱动电路包括多个扫描移位寄存器单元，一对互补时钟信号线和水平启动信号发生器。 每个扫描移位寄存器单元包括双向电路，耦合到双向电路的移位寄存器，耦合到移位寄存器的传输门，以及耦合到传输门的数据线。 互补时钟信号线耦合到移位寄存器。 水平启动信号发生器向第一和随后的扫描移位寄存器单元中的双向电路提供水平启动信号。 每个扫描移位寄存器单元中的移位寄存器向下一个扫描移位寄存器单元中的双向电路提供输出信号。 每个扫描移位寄存器单元中的双向电路还从下一个扫描移位寄存器单元中的移位寄存器接收输出信号。

公开(公告)号：US20090284483A1

公开(公告)日：2009-11-19

申请号：US12255878

申请日：2008-10-22

Applicant: Yu-Hsin Ting ,  Chee-Wai Lau ,  Ming-Tien Lin ,  Chung-Lung Li ,  Heng-Sheng Chou

Inventor： Yu-Hsin Ting ,  Chee-Wai Lau ,  Ming-Tien Lin ,  Chung-Lung Li ,  Heng-Sheng Chou

IPC: G06F3/041

CPC classification number: G06F3/044 ,  G06F3/0412

Abstract: A display device and method having a sensing function is described. The device includes a liquid crystal display (LCD) panel and plural sense lines. The LCD panel includes a plurality of data lines and a plurality of gate lines. Each of the data lines is connected electrically to a plurality of left pixels and a plurality of right pixels. The sense line is disposed between each two adjacent data lines, and each of the sense lines is configured to be parallel to the data lines and perpendicular to the gate lines. The sense lines are used to transmit touch signals.

Abstract translation: 描述具有感测功能的显示装置和方法。 该装置包括液晶显示器（LCD）面板和多条感测线。 LCD面板包括多条数据线和多条栅极线。 每条数据线与多个左像素和多个右像素电连接。 感测线设置在每个两个相邻数据线之间，并且每个感测线被配置为平行于数据线并垂直于栅极线。 感测线用于传输触摸信号。

公开(公告)号：US08115754B2

公开(公告)日：2012-02-14

申请号：US12413835

申请日：2009-03-30

Applicant: Chung-Lin Fu ,  Fu-Yuan Liou ,  Yu-Hsin Ting ,  Shu-Huan Hsieh

Inventor： Chung-Lin Fu ,  Fu-Yuan Liou ,  Yu-Hsin Ting ,  Shu-Huan Hsieh

IPC: G06F3/038

CPC classification number: G09G3/3611 ,  G09G2310/0202 ,  G09G2310/0224 ,  G09G2320/0209

Abstract: A data line driving method adapted in a display panel driver circuit is provided. The display panel driver circuit comprises a plurality rows of gate lines and a plurality of data driver stages each corresponding to a data line group, wherein the data line driving method comprises the steps of: turning on the data driver stages in a first sequential order to input a first frame data in the data line groups corresponding to the data driver stages in each gate line activation time within a first frame period; and turning on the data driver stages in a second sequential order which is opposed to the first sequential order to input a second frame data in the data line groups corresponding to the data driver stages in each gate line activation time within a second frame period; wherein the first and the second frame period are two interlaced periods next to each other.

Abstract translation: 提供一种适用于显示面板驱动电路的数据线驱动方法。 显示面板驱动电路包括多行栅极线和多个对应于数据线组的数据驱动器级，其中数据线驱动方法包括以下步骤：以第一顺序接通数据驱动器级，以 在第一帧周期内的每个栅极线激活时间内，在对应于数据驱动器级的数据线组中输入第一帧数据; 并以与第一顺序顺序相反的第二顺序顺序接通数据驱动器级，以在第二帧周期内的每个栅极线激活时间内输入与数据驱动器级对应的数据线组中的第二帧数据; 其中第一和第二帧周期是彼此相邻的两个隔行周期。

公开(公告)号：US20100277462A1

公开(公告)日：2010-11-04

申请号：US12490302

申请日：2009-06-23

Applicant: Yu-Hsin Ting ,  Tsao-Wen Lu

Inventor： Yu-Hsin Ting ,  Tsao-Wen Lu

IPC: G09G5/00

CPC classification number: G09G5/00 ,  G09G2330/027

Abstract: A display and a method for eliminating a residual image thereof are provided. The method includes detecting a status of an electric power supplied by a power supply unit of the display when the display is in the power on state; and coupling the electric power to a reference voltage when the electric power is suddenly terminated so as to accelerately discharge charges remaining on the electric power.

Abstract translation: 提供了一种用于消除其残留图像的显示器和方法。 该方法包括当显示器处于通电状态时检测由显示器的电源单元提供的电力的状态; 并且当电力突然终止时将电力耦合到参考电压，以便加速放电剩余在电力上的电荷。

公开(公告)号：US20100110045A1

公开(公告)日：2010-05-06

申请号：US12413835

申请日：2009-03-30

Applicant: Chung-Lin Fu ,  Fu-Yuan Liou ,  Yu-Hsin Ting ,  Shu-Huan Hsieh

Inventor： Chung-Lin Fu ,  Fu-Yuan Liou ,  Yu-Hsin Ting ,  Shu-Huan Hsieh

IPC: G06F3/038

CPC classification number: G09G3/3611 ,  G09G2310/0202 ,  G09G2310/0224 ,  G09G2320/0209

Abstract: A data line driving method adapted in a display panel driver circuit is provided. The display panel driver circuit comprises a plurality rows of gate lines and a plurality of data driver stages each corresponding to a data line group, wherein the data line driving method comprises the steps of: turning on the data driver stages in a first sequential order to input a first frame data in the data line groups corresponding to the data driver stages in each gate line activation time within a first frame period; and turning on the data driver stages in a second sequential order which is opposed to the first sequential order to input a second frame data in the data line groups corresponding to the data driver stages in each gate line activation time within a second frame period; wherein the first and the second frame period are two interlaced periods next to each other.

Abstract translation: 提供一种适用于显示面板驱动电路的数据线驱动方法。 显示面板驱动电路包括多行栅极线和多个对应于数据线组的数据驱动器级，其中数据线驱动方法包括以下步骤：以第一顺序接通数据驱动器级，以 在第一帧周期内的每个栅极线激活时间内，在对应于数据驱动器级的数据线组中输入第一帧数据; 并以与第一顺序顺序相反的第二顺序顺序接通数据驱动器级，以在第二帧周期内的每个栅极线激活时间内输入与数据驱动器级对应的数据线组中的第二帧数据; 其中第一和第二帧周期是彼此相邻的两个隔行周期。

公开(公告)号：US20070148563A1

公开(公告)日：2007-06-28

申请号：US11426388

申请日：2006-06-26

Applicant: Yen-Heng Huang ,  Yu-Wei Liu ,  Yu-Hsin Ting ,  Kuo-Yu Huang

Inventor： Yen-Heng Huang ,  Yu-Wei Liu ,  Yu-Hsin Ting ,  Kuo-Yu Huang

IPC: G02B5/20

CPC classification number: G02B5/201 ,  G02B5/223 ,  G02F1/133516

Abstract: A color filter and a method for fabricating the same. At least one conductive film is provided above a light shielding layer between R/G/B color filter units. The conductive film is electrically connected to an electrode layer, thereby reducing the resistance thereof.

Abstract translation: 滤色器及其制造方法。 在R / G / B滤色器单元之间的遮光层上方设置至少一个导电膜。 导电膜电连接到电极层，从而降低其电阻。