Controlled tapered angle etching process for fabricating optical
integrated circuits
    2.
    发明授权
    Controlled tapered angle etching process for fabricating optical integrated circuits 失效
    用于制造光集成电路的受控锥形蚀刻工艺

    公开(公告)号:US5473710A

    公开(公告)日:1995-12-05

    申请号:US134420

    申请日:1993-10-08

    IPC分类号: G02B6/12 G02B6/136 G02B6/42

    摘要: The present invention discloses an OIC fabrication system which includes a tapered angle computing means for computing a tapered angle for aching a required coupling efficiency. The fabrication system also includes a fabrication control means which includes a tabulated fabricating parameter database for determining and controlling a plurality of fabricating parameters. The fabrication system also includes an etching system which receives a plurality of control signals from the fabrication controlling means to carry out the etching process to form a tapered etching angle such that the optical coupling efficiency can be achieved.

    摘要翻译: 本发明公开了一种OIC制造系统,其包括锥形角度计算装置,用于计算用于刺激所需耦合效率的锥角。 制造系统还包括制造控制装置,其包括用于确定和控制多个制造参数的制表参数数据库。 制造系统还包括蚀刻系统,其接收来自制造控制装置的多个控制信号,以执行蚀刻工艺以形成锥形刻蚀角,使得可以实现光耦合效率。

    Microchannel-element assembly and preparation method thereof
    3.
    发明授权
    Microchannel-element assembly and preparation method thereof 有权
    微通道元件装配及其制备方法

    公开(公告)号:US6100107A

    公开(公告)日:2000-08-08

    申请号:US137447

    申请日:1998-08-06

    CPC分类号: B81B1/00

    摘要: A preparation method for an integrated assembly of a microchannel and an element is disclosed. In the preparation method of this invention, an element is prepared between a substrate and a sacrificial layer. Two protection layers, which are resistant to etchant for said substrate and said sacrificial layer, are prepared to isolate said element from its ambient environment. Said sacrificial layer defines an area to be etched off such that a microchannel may be formed. A coating layer with etching windows is then prepared on said sacrificial layer and the assembly is etched in an etchant to etch off said sacrificial layer and an area of said substrate beneath said sacrificial layer. An integrated assembly of a closed microchannel and an element is then accomplished. In the invented method, no bonding process is necessary and the integrated assembly so prepared has a planarization surface. This invention also disclosed a microchannel-element assembly prepared under the method of this invention.

    摘要翻译: 公开了一种用于微通道和元件的集成组装的制备方法。 在本发明的制备方法中,在衬底和牺牲层之间制备元件。 准备两个保护层,其耐蚀刻所述衬底和所述牺牲层,以将所述元件与其周围环境隔离。 所述牺牲层限定要被蚀刻的区域,使得可以形成微通道。 然后在所述牺牲层上制备具有蚀刻窗口的涂层,并且在蚀刻剂中蚀刻组件以蚀刻所述牺牲层和所述牺牲层下面的所述衬底的区域。 然后完成闭合的微通道和元件的集成组件。 在本发明的方法中,不需要接合工艺,并且如此制备的集成组件具有平坦化表面。 本发明还公开了根据本发明的方法制备的微通道元件组件。

    Method of automatically coupling between a fiber and an optical waveguide
    4.
    发明授权
    Method of automatically coupling between a fiber and an optical waveguide 失效
    纤维和光波导之间自动耦合的方法

    公开(公告)号:US5600745A

    公开(公告)日:1997-02-04

    申请号:US598660

    申请日:1996-02-08

    CPC分类号: G02B6/30 G02B6/132

    摘要: A method of automatically coupling between a fiber and an optical waveguide is disclosed. Such a scheme is achieved by the property of the different etching rate in the various wafer direction on a semiconductor material, especial silicon, and the shrinking property of the glass soot formed by a flame hydrolysis deposition technique during a high temperature consolidation process, for improving aligning accuracy. The manufacturing process of the method is described below. First, a waveguide buffer layer is formed on a semiconductor substrate, then a waveguide layer is formed on the semiconductor substrate and the waveguide buffer layer. A part of the waveguide is manipulated to the planar optical waveguide, meanwhile, several windows which lead to the I/O end of the planar waveguide are formed on the other waveguide layer. The semiconductor substrate beneath the windows is etched anisotropically to form several aligning grooves. The lateral faces of these grooves and the surface of the semiconductor substrate can constitute a fixed angle.

    摘要翻译: 公开了一种在光纤和光波导之间自动耦合的方法。 通过在高温固化处理中通过火焰水解沉积技术形成的玻璃烟炱在半导体材料,特殊硅上的各种晶片方向上的不同蚀刻速率的性质来实现这种方案,以改善 对准精度。 该方法的制造过程如下所述。 首先,在半导体衬底上形成波导缓冲层,然后在半导体衬底和波导缓冲层上形成波导层。 波导的一部分被操纵到平面光波导,同时,导致平面波导的I / O端的几个窗口形成在另一个波导层上。 窗口下方的半导体衬底被各向异性地蚀刻以形成几个对准槽。 这些沟槽和半导体衬底的表面的侧面可以构成固定的角度。

    Deep groove structure for semiconductors
    5.
    发明授权
    Deep groove structure for semiconductors 失效
    半导体深槽结构

    公开(公告)号:US06025209A

    公开(公告)日:2000-02-15

    申请号:US909090

    申请日:1997-08-12

    摘要: Deep groove structure for semiconductors comprising a semiconductor substrate, a groove or a cavity formed in said semiconductor substrate and a suspending glass membrane formed on the groove or deep cavity, prepared by a flame hydrolysis deposition process. The suspending glass membrane functions as a planarization structure and has surface at the same level of the surface of the semiconductor substrate. The present invention also discloses a method to prepare the deep groove structure.

    摘要翻译: 用于半导体的深槽结构包括半导体衬底,形成在所述半导体衬底中的凹槽或腔,以及通过火焰水解沉积工艺制备的形成在凹槽或深腔上的悬浮玻璃膜。 悬浮玻璃膜用作平坦化结构,并且具有与半导体基板的表面相同水平面的表面。 本发明还公开了一种制备深沟槽结构的方法。