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9 条记录 (耗时 0.018 秒)

    Global Bit Line Restore Timing Scheme and Circuit
    1.
    发明申请
    Global Bit Line Restore Timing Scheme and Circuit 失效
    全局位线恢复时序方案和电路

    公开(公告)号：US20070058421A1

    公开(公告)日：2007-03-15

    申请号：US11554072

    申请日：2006-10-30

    申请人： Yuen Chan ,  Ryan Freese ,  Antonio Pelella ,  Uma Srinivasan ,  Arthur Tuminaro ,  Jatinder Wadhwa

    发明人： Yuen Chan ,  Ryan Freese ,  Antonio Pelella ,  Uma Srinivasan ,  Arthur Tuminaro ,  Jatinder Wadhwa

    IPC分类号： G11C11/00

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/417

    摘要： A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck1), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

    摘要翻译： 多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动工作解码线，从而消除了字线选择的任何种族问题。 该系统允许全局位选择（或列选择）通过释放复位信号（具有最早到达的阵列时钟ck 1）来快速激活，同时保证使用位解码系统几乎完美的跟踪。 这允许最广泛的写入窗口; 全局列中最早发布预充电选择，仅在位解码系统被禁用后进行复位。

    Local bit select with suppression of fast read before write
    3.
    发明申请
    Local bit select with suppression of fast read before write 失效
    本地位选择与写入前禁止快速读取

    公开(公告)号：US20060176729A1

    公开(公告)日：2006-08-10

    申请号：US11054402

    申请日：2005-02-09

    申请人： Yuen Chan ,  Ryan Freese ,  Antonio Pelella ,  Arthur Tuminaro

    发明人： Yuen Chan ,  Ryan Freese ,  Antonio Pelella ,  Arthur Tuminaro

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

    摘要： A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors. Separate read and write global “bit line” pairs allow the read and write performance to be optimized independently

    摘要翻译： 多米诺SRAM提供有有源上拉PFET器件，它们淹没“读写速度慢但读取速度非常快”，并允许单元从定时不匹配情况中恢复。 这种方法允许传统的“位选择”钳位通过“有线或”PFET上拉晶体管主动地控制“局部选择”。 单独的读写全局“位线”对可以独立优化读写性能

    Global bit line restore timing scheme and circuit
    5.
    发明申请
    Global bit line restore timing scheme and circuit 失效
    全局位线恢复时序方案和电路

    公开(公告)号：US20060176730A1

    公开(公告)日：2006-08-10

    申请号：US11054479

    申请日：2005-02-09

    申请人： Yuen Chan ,  Ryan Freese ,  Antonio Pelella ,  Uma Srinivasan ,  Arthur Tuminaro ,  Jatinder Wadhwa

    发明人： Yuen Chan ,  Ryan Freese ,  Antonio Pelella ,  Uma Srinivasan ,  Arthur Tuminaro ,  Jatinder Wadhwa

    IPC分类号： G11C11/00

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/417

    摘要： A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

    摘要翻译： 多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动字解码线，从而消除了字线选择的任何种族问题。 该系统允许全局位选择（或列选择）通过释放复位信号（具有最早到达的阵列时钟ckl）来快速激活，同时保证与位解码系统几乎完美的跟踪。 这允许最广泛的写入窗口; 全局列中最早发布预充电选择，仅在位解码系统被禁用后进行复位。

    Single clock dynamic compare circuit
    7.
    发明授权
    Single clock dynamic compare circuit 有权
    单时钟动态比较电路

    公开(公告)号：US08233331B2

    公开(公告)日：2012-07-31

    申请号：US12792475

    申请日：2010-06-02

    申请人： Yuen H. Chan ,  Antonio R. Pelella ,  Richard E. Serton ,  Arthur Tuminaro

    发明人： Yuen H. Chan ,  Antonio R. Pelella ,  Richard E. Serton ,  Arthur Tuminaro

    IPC分类号： G11C7/06

    CPC分类号： H03K19/20

    摘要： A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.

    摘要翻译： 用于比较第一数据字与第二数据字的比较电路包括多个子电路，每个子电路具有两位静态比较级和动态复合逻辑级; 响应于子电路的相应输出的动态比较节点; 以及输出锁存器，其根据动态比较节点的逻辑状态捕获比较结果。 在示例性实施例中，本地时钟发生器提供单个控制时钟信号，用于对输出锁存器进行计时，动态比较节点的预充电以及子电路的动态复合逻辑级的计时。

    Self timed bit and read/write pulse stretchers
    8.
    发明申请
    Self timed bit and read/write pulse stretchers 有权
    自定时位和读/写脉冲担架

    公开(公告)号：US20050128855A1

    公开(公告)日：2005-06-16

    申请号：US10736415

    申请日：2003-12-15

    申请人： Rajiv Joshi ,  Arthur Tuminaro

    发明人： Rajiv Joshi ,  Arthur Tuminaro

    IPC分类号： G11C7/22 ,  G11C8/00 ,  G11C11/419

    CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

    摘要： Bit and write decode/drivers, a random access memory (RAM) including the decode/drivers and an IC with a static RAM (SRAM) including the decode/drivers. The decode/drivers are clocked by a local clock and each produce access pulses wider than corresponding clock pulses. The bit decode/driver produces bit select pulses that are wider than a word select pulse and the write decode/driver produces write pulses that are wider than the bit select pulses for stable self timed RAM write accesses.

    摘要翻译： 位和写入解码/驱动器，包括解码/驱动器的随机存取存储器（RAM）和具有包括解码/驱动器的静态RAM（SRAM）的IC。 解码/驱动器由本地时钟计时，并产生比对应的时钟脉冲宽的访问脉冲。 位解码/驱动器产生比字选择脉冲宽的位选择脉冲，写解码/驱动器产生比用于稳定自定时RAM写访问的位选择脉冲宽的写入脉冲。

    SINGLE CLOCK DYNAMIC COMPARE CIRCUIT
    9.
    发明申请
    SINGLE CLOCK DYNAMIC COMPARE CIRCUIT 有权
    单时钟动态比较电路

    公开(公告)号：US20110298500A1

    公开(公告)日：2011-12-08

    申请号：US12792475

    申请日：2010-06-02

    申请人： Yuen H. Chan ,  Antonio R. Pelella ,  Richard E. Serton ,  Arthur Tuminaro

    发明人： Yuen H. Chan ,  Antonio R. Pelella ,  Richard E. Serton ,  Arthur Tuminaro

    IPC分类号： H03K5/00

    CPC分类号： H03K19/20

    摘要： A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.

    摘要翻译： 用于比较第一数据字与第二数据字的比较电路包括多个子电路，每个子电路具有两位静态比较级和动态复合逻辑级; 响应于子电路的相应输出的动态比较节点; 以及输出锁存器，其根据动态比较节点的逻辑状态捕获比较结果。 在示例性实施例中，本地时钟发生器提供单个控制时钟信号，用于对输出锁存器进行计时，动态比较节点的预充电以及子电路的动态复合逻辑级的计时。