COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    化合物半导体器件及其制造方法

    公开(公告)号:US20120241758A1

    公开(公告)日:2012-09-27

    申请号:US13493293

    申请日:2012-06-11

    IPC分类号: H01L29/20 H01L21/336

    摘要: A compound semiconductor device is provided with a first nitride semiconductor layer of a first conductivity type, a second nitride semiconductor layer of the first conductivity type which is formed over the first nitride semiconctor layer and being in contact with the first nitride semiconductor layer, a third nitride semiconductor layer of a second conductivity type being in contact with the second nitride semiconductor layer, a fourth nitride semiconductor layer of the first conductivity type being in contact with the third nitride semiconductor layer, and an insulating film insulating the first nitride semiconductor layer and the fourth nitride, semiconductor layer from each other. A source electrode is positioned inside an Outer edge of the insulating film in planar view.

    摘要翻译: 化合物半导体器件设置有第一导电类型的第一氮化物半导体层,第一导电类型的第二氮化物半导体层,其形成在第一氮化物半导体层上并与第一氮化物半导体层接触,第三导电类型的第三氮化物半导体层, 与第二氮化物半导体层接触的第二导电类型的氮化物半导体层,与第三氮化物半导体层接触的第一导电类型的第四氮化物半导体层和将第一氮化物半导体层和 第四氮化物,半导体层。 在平面图中,源电极位于绝缘膜的外边缘的内侧。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号:US20130075750A1

    公开(公告)日:2013-03-28

    申请号:US13572806

    申请日:2012-08-13

    申请人: Yuichi MINOURA

    发明人: Yuichi MINOURA

    IPC分类号: H01L29/78 H01L21/20

    摘要: A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed on the second semiconductor layer. The third semiconductor layer is formed with a semiconductor material doped with a p-type impurity element. In the third semiconductor layer, a p-type area is formed immediately below the gate electrode, and a high resistance area having a higher resistance than the p-type area is formed in an area other than the p-type area.

    摘要翻译: 半导体器件包括形成在衬底上的第一半导体层; 形成在所述第一半导体层上的第二半导体层; 形成在所述第二半导体层上的第三半导体层; 形成在所述第三半导体层上的栅电极; 以及形成在第二半导体层上的源电极和漏电极。 第三半导体层由掺杂有p型杂质元素的半导体材料形成。 在第三半导体层中,在栅电极的正下方形成p型区域,在p型区域以外的区域形成具有比p型区域高的电阻的高电阻区域。