公开(公告)号：US06754805B1

公开(公告)日：2004-06-22

申请号：US09633831

申请日：2000-08-07

申请人： Yujen Juan

发明人： Yujen Juan

IPC分类号： G06F1700

CPC分类号： G06F15/7867

摘要： An improved mechanism for performing different types of digital signal processing functions, including correlation, sorting, and filtering operations. The mechanism includes a plurality of computational cells which can be dynamically configured (and reconfigured) in parallel to perform the different types of digital signal processing functions. Preferably, the computation cells carry out such digital signal processing operations in parallel without the need for extensive iteration. Such parallel configuration and subsequent parallel processing operations provide improved computational performance.

摘要翻译： 一种用于执行不同类型的数字信号处理功能的改进机制，包括相关性，排序和过滤操作。 该机构包括可以并行地动态配置（并重新配置）多个计算单元，以执行不同类型的数字信号处理功能。 优选地，计算单元并行执行这样的数字信号处理操作，而不需要广泛的迭代。 这种并行配置和随后的并行处理操作提供了改进的计算性能。

公开(公告)号：US06401106B1

公开(公告)日：2002-06-04

申请号：US09633693

申请日：2000-08-07

申请人： Yujen Juan

发明人： Yujen Juan

IPC分类号： G06F1715

CPC分类号： G06F17/15

摘要： Methods and apparatus for implementing an enhanced digital signal processor through the addition of modular computation units which can be operated in parallel are described. In various embodiments the computation units are implemented as configurable computation cells which are arranged to form a computation engine which supplements conventional DSP circuitry. The computation cells can be used to perform frequently used DSP functions such a cross-correlation, sorting, FIR filtering quickly without the need for extensive iterative processing. By using the computation cells of the present invention in parallel, the computation of common DSP functions can be performed quickly and resulting in improvements in DSP performance as compared to convention DSPs.

摘要翻译： 描述了通过添加可以并行操作的模块化计算单元来实现增强型数字信号处理器的方法和装置。 在各种实施例中，计算单元被实现为可配置的计算单元，其被配置成形成补充常规DSP电路的计算引擎。 计算单元可用于快速执行频繁使用的DSP功能，如互相关，排序，FIR滤波，无需广泛的迭代处理。 通过并行地使用本发明的计算单元，与常规DSP相比，可以快速执行公共DSP功能的计算并且导致DSP性能的提高。

公开(公告)号：US5642382A

公开(公告)日：1997-06-24

申请号：US396839

申请日：1995-03-01

申请人： Yujen Juan

发明人： Yujen Juan

IPC分类号： H03H17/02 ,  H03H17/06 ,  H04L25/03 ,  H03H7/30

CPC分类号： H03H17/0292 ,  H03H17/0294 ,  H03H17/06 ,  H04L25/03038 ,  H03H2218/085

摘要： Methods and apparatus for providing implementation efficient adaptive equalizers suitable for use with QAM and/or VSB signals are disclosed. Finite impulse response ("FIR") filters are used to implement the disclosed adaptive equalizers. A plurality of arithmetic operator sharing techniques are disclosed for reducing the number of arithmetic operators required to implement the adaptive equalizers. In addition, methods of reconfiguring the arithmetic operators used to implement a QAM equalizer so that they can be used to implement a VSB equalizer circuit are disclosed. Methods of the present invention use multiplexers to reconfigure the FIR filters from a complex decimating FIR filter for use during QAM operation, to a half complex feedforward FIR filter and a real decision feedback FIR filter suitable for use during VSB mode operation of the equalizer circuit of the present invention. Using the methods of the present invention it is possible to implement a 256-tap FIR filter using only 64 sets of arithmetic operators. The adaptive equalizer of the present invention may be used in a demodulator for demodulating QAM and/or VSB signals.

摘要翻译： 公开了用于提供适用于QAM和/或VSB信号的实现高效自适应均衡器的方法和装置。 有限脉冲响应（“FIR”）滤波器用于实现所公开的自适应均衡器。 公开了用于减少实现自适应均衡器所需的算术运算器的数量的多个算术运算符共享技术。 此外，公开了重新配置用于实现QAM均衡器的算术运算器以使得它们可以用于实现VSB均衡器电路的方法。 本发明的方法使用多路复用器从QAM操作期间使用的复数抽取FIR滤波器重新配置FIR滤波器到半复合前馈FIR滤波器和适用于均衡器电路的VSB模式操作期间的真实决策反馈FIR滤波器 本发明。 使用本发明的方法，可以实现仅使用64组算术运算符的256抽头FIR滤波器。 本发明的自适应均衡器可用于解调QAM和/或VSB信号的解调器。