公开(公告)号：US20110087716A1

公开(公告)日：2011-04-14

申请号：US12637771

申请日：2009-12-15

申请人： Kung-Piao Huang

发明人： Kung-Piao Huang

IPC分类号： G06F17/10

CPC分类号： H03H17/0294 ,  H03H17/0223 ,  H03H17/0621 ,  H03H2218/085

摘要： A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal.

摘要翻译： 公开了一种包括抗混叠滤波器，多个乘法器模块，折叠块和数据编辑器的多速率滤波器组。 抗混叠滤波器接收抗混叠输入信号。 乘法器模块模块接收原始信号并顺序产生多个处理的信号。 乘法器模块还接收多个块输入信号和选择信号。 每个乘法器块模块根据选择信号配置成抽取块或扩展抗混叠滤波器。 折叠块接收选择信号和折叠输入信号，并产生折叠块输出信号。 数据编辑器接收和组合折叠块输出信号和多路复用器模块和抗混叠滤波器的输出，并产生抗混叠滤波器输出信号。

公开(公告)号：US20070276892A1

公开(公告)日：2007-11-29

申请号：US11833030

申请日：2007-08-02

申请人： Hidekuni YOMO ,  Yoshinori KUNIEDA ,  Yuuri YAMAMOTO

发明人： Hidekuni YOMO ,  Yoshinori KUNIEDA ,  Yuuri YAMAMOTO

IPC分类号： G06F17/10

CPC分类号： H03H17/0657 ,  H03H17/0223 ,  H03H17/0229 ,  H03H17/06 ,  H03H17/0621 ,  H03H2218/085

摘要： An A/D conversion section performs oversampling on an analog signal at a rate M times a symbol rate to convert the analog signal into a digital signal. A FIR filtering section has two delay-element sequences, each with a plurality of delay elements. The two delay-element sequences have different delay directions, i.e., a forward direction and a reverse direction. The delay directions can be switched, and according to a finite impulse response train having such delay-element sequences, a convolutional calculation is performed. A phase determining section determines a phase used in making a decision in a decision section. The decision section makes a decision on a filtered signal using the phase determined in the phase determining section to generate bit data. A digital signal receiving apparatus is thus achieved which determines a phase with a high accuracy without increasing the oversampling number, and performs a fast calculation while having a reduced circuitry scale.

摘要翻译： A / D转换部分以符号速率M倍的模拟信号执行过采样，以将模拟信号转换为数字信号。 FIR滤波部分具有两个具有多个延迟元件的延迟元件序列。 两个延迟元件序列具有不同的延迟方向，即正向和反向。 可以切换延迟方向，并且根据具有这种延迟元件序列的有限脉冲响应列，进行卷积计算。 相位确定部确定在判定部中作出判定所使用的相位。 决定部分使用在相位确定部分中确定的相位来对滤波信号做出决定以产生位数据。 因此，实现了数字信号接收装置，其在不增加过采样数量的情况下确定高精度的相位，并且在具有减小的电路规模的情况下执行快速计算。

公开(公告)号：US5642382A

公开(公告)日：1997-06-24

申请号：US396839

申请日：1995-03-01

申请人： Yujen Juan

发明人： Yujen Juan

IPC分类号： H03H17/02 ,  H03H17/06 ,  H04L25/03 ,  H03H7/30

CPC分类号： H03H17/0292 ,  H03H17/0294 ,  H03H17/06 ,  H04L25/03038 ,  H03H2218/085

摘要： Methods and apparatus for providing implementation efficient adaptive equalizers suitable for use with QAM and/or VSB signals are disclosed. Finite impulse response ("FIR") filters are used to implement the disclosed adaptive equalizers. A plurality of arithmetic operator sharing techniques are disclosed for reducing the number of arithmetic operators required to implement the adaptive equalizers. In addition, methods of reconfiguring the arithmetic operators used to implement a QAM equalizer so that they can be used to implement a VSB equalizer circuit are disclosed. Methods of the present invention use multiplexers to reconfigure the FIR filters from a complex decimating FIR filter for use during QAM operation, to a half complex feedforward FIR filter and a real decision feedback FIR filter suitable for use during VSB mode operation of the equalizer circuit of the present invention. Using the methods of the present invention it is possible to implement a 256-tap FIR filter using only 64 sets of arithmetic operators. The adaptive equalizer of the present invention may be used in a demodulator for demodulating QAM and/or VSB signals.

摘要翻译： 公开了用于提供适用于QAM和/或VSB信号的实现高效自适应均衡器的方法和装置。 有限脉冲响应（“FIR”）滤波器用于实现所公开的自适应均衡器。 公开了用于减少实现自适应均衡器所需的算术运算器的数量的多个算术运算符共享技术。 此外，公开了重新配置用于实现QAM均衡器的算术运算器以使得它们可以用于实现VSB均衡器电路的方法。 本发明的方法使用多路复用器从QAM操作期间使用的复数抽取FIR滤波器重新配置FIR滤波器到半复合前馈FIR滤波器和适用于均衡器电路的VSB模式操作期间的真实决策反馈FIR滤波器 本发明。 使用本发明的方法，可以实现仅使用64组算术运算符的256抽头FIR滤波器。 本发明的自适应均衡器可用于解调QAM和/或VSB信号的解调器。

公开(公告)号：US20150019607A1

公开(公告)日：2015-01-15

申请号：US14120351

申请日：2014-05-14

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： MI JEONG PARK ,  JANG HONG CHOI ,  IK SOO EO

IPC分类号： G06F17/17

CPC分类号： H03H17/0657 ,  H03H2218/085

摘要： Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value. Thus, continuity of output data can be guaranteed, and hardware can be shared by using time assignment algorithm so that a total size of the interpolation filter can be reduced.

摘要翻译： 公开了一种基于时间分配算法的内插滤波器。 内插滤波器包括使能信号产生部分产生用于内插滤波器的操作的使能信号，产生输入值的输入值产生部分，基于第一使能信号和第一输入值产生第一输出值的第一计算部分， 第二计算部分，基于第二使能信号和第二输入值产生第二输出值;以及输出值选择部分，选择所述第一输出值和所述第二输出值中的最终输出值。 因此，可以保证输出数据的连续性，并且可以通过使用时间分配算法来共享硬件，使得可以减少内插滤波器的总大小。

公开(公告)号：US20090080581A1

公开(公告)日：2009-03-26

申请号：US12236342

申请日：2008-09-23

申请人： Axel Schuur ,  Ann P. Shen ,  Ali Tabatabaei

发明人： Axel Schuur ,  Ann P. Shen ,  Ali Tabatabaei

IPC分类号： H04B1/10

CPC分类号： H03H17/045 ,  H03H17/0292 ,  H03H2218/085

摘要： At least some of the arithmetic operations of a filter or other digital process can be performed time sequentially, which may allow the arithmetic elements for the filter or other digital process to be used multiple times for multiple operations.

摘要翻译： 滤波器或其他数字处理的算术运算的至少一些可以顺序执行，这可以允许用于滤波器或其他数字处理的算术元件多次用于多个操作。

公开(公告)号：US20080240220A1

公开(公告)日：2008-10-02

申请号：US12023377

申请日：2008-01-31

申请人： Bjoern ELLERMEYER

发明人： Bjoern ELLERMEYER

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H03H17/0292 ,  H03H17/0275 ,  H03H17/0621 ,  H03H17/0664 ,  H03H2218/085

摘要： Digital filter, comprising a multiplier configured to generate an intermediate signal, wherein said intermediate signal is generated by multiplying an input signal with a filter coefficient signal, wherein said multiplier is operated at a clock rate and said input signal has a sampling rate, wherein said clock rate is higher than said sampling rate; a first buffer configured to supply said filter coefficient signal to said multiplier at said clock rate, wherein said filter coefficient signal represents N filter coefficients in a periodic order, wherein N denotes the order of said digital filter; a second buffer configured to buffer N/2 samples of an intermediate output signal and to generate a respective time delayed intermediate output signal; and an adder configured to generate said intermediate output signal or an output signal of said digital filter based on an addition of said time delayed intermediate output signal and said intermediate signal.

摘要翻译： 数字滤波器，包括被配置为产生中间信号的乘法器，其中所述中间信号通过将输入信号与滤波器系数信号相乘而产生，其中所述乘法器以时钟速率操作，并且所述输入信号具有采样率，其中所述 时钟频率高于所述采样率; 第一缓冲器，被配置为以所述时钟速率将所述滤波器系数信号提供给所述乘法器，其中所述滤波器系数信号以周期顺序表示N个滤波器系数，其中N表示所述数字滤波器的阶数; 第二缓冲器，被配置为缓冲中间输出信号的N / 2采样并产生相应的时间延迟的中间输出信号; 以及加法器，被配置为基于所述延时中间输出信号和所述中间信号的相加来产生所述中间输出信号或所述数字滤波器的输出信号。

公开(公告)号：US20030195913A1

公开(公告)日：2003-10-16

申请号：US10118635

申请日：2002-04-10

发明人： Charles Douglas Murphy

IPC分类号： G06F007/52

CPC分类号： G06F7/5334 ,  H03H17/0226 ,  H03H2017/0232 ,  H03H2218/085

摘要： A machine or method used for reducing the implementation cost of digital filters that use multiplication operations. For each new input, a small look-up table of products is computed and stored. Weighting of the inputs when computing digital filter outputs can be accomplished using look-up table access, shifting, and addition. The invention can be used for constant filters or for adaptive filters. With constant filter coefficients, a small look-up table which exploits the properties of the various coefficient representations as a group is possible. With adaptive filters, a larger table may be needed, but can be used to reduce the multiplication cost of both filter output computation and filter adaptation. The invention is particularly useful in technologies where general multiplication is costly, such as field programmable gate arrays, application specific integrated circuits, and software running on general-purpose microprocessors. The invention can be used for high-precision computations without the need for large look-up tables. The invention can lead to digital filter implementation with reduced chip space, computation time, and power consumptions relative to implementations that do not share processing among multipliers.

摘要翻译： 用于降低使用乘法运算的数字滤波器的实现成本的机器或方法。 对于每个新的输入，计算并存储一个小的产品查询表。 计算数字滤波器输出时输入的权重可以通过查询表访问，移位和相加来完成。 本发明可用于恒定滤波器或自适应滤波器。 利用恒定的滤波器系数，可以将利用各种系数表示的属性作为一组的小型查找表是可能的。 使用自适应滤波器，可能需要较大的表，但可用于降低滤波器输出计算和滤波器适配的乘法成本。 本发明特别适用于一般乘法费用高昂的技术，例如现场可编程门阵列，专用集成电路和在通用微处理器上运行的软件。 本发明可用于高精度计算，而不需要大型查找表。 相对于不在乘法器之间共享处理的实现，本发明可以导致数字滤波器实现，减少了芯片空间，计算时间和功耗。

公开(公告)号：US6108681A

公开(公告)日：2000-08-22

申请号：US31698

申请日：1998-02-27

申请人： Karl Wittig ,  Gene Turkenich

发明人： Karl Wittig ,  Gene Turkenich

IPC分类号： H03H21/00 ,  H03H17/02 ,  H03H17/06 ,  G06F17/10

CPC分类号： H03H17/0294 ,  H03H17/0225 ,  H03H17/0292 ,  H03H2218/085

摘要： A digital filter has a filter cell for generating processed data. The digital filter cell includes plurality of coefficient registers which are arranged to circulate a plurality of coefficient values that correspond to a plurality of coefficients such that each of the plurality of coefficients is output once during a predetermined period. One or more data registers are arranged to circulate a data value for a time which is at least as long as the predetermined period such that the data value is output each time that a different one of the plurality of coefficients is output. A circuit receives each output data value and each output coefficient and generates processed data by processing each output data value with each output coefficient.

摘要翻译： 数字滤波器具有用于产生处理数据的滤波器单元。 数字滤波器单元包括多个系数寄存器，其被布置为循环多个系数值，所述多个系数值对应于多个系数，使得在预定周期期间多个系数中的每一个系数被输出一次。 布置一个或多个数据寄存器以使数据值循环至少等于预定周期的时间，使得每次输出多个系数中的不同系数时输出数据值。 电路接收每个输出数据值和每个输出系数，并通过用每个输出系数处理每个输出数据值来产生处理数据。

公开(公告)号：US5317529A

公开(公告)日：1994-05-31

申请号：US859208

申请日：1992-03-27

申请人： Eiichi Teraoka ,  Toru Kengaku ,  Hiroichi Ishida

发明人： Eiichi Teraoka ,  Toru Kengaku ,  Hiroichi Ishida

IPC分类号： H03M1/00 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H03M3/00 ,  G06F15/31

CPC分类号： H03H17/0657 ,  H03H17/0664 ,  H03H17/0685 ,  H03H2218/08 ,  H03H2218/085

摘要： An A/D-D/A converting apparatus, in which a multiplier is omitted by storing the multiplied result of a filter coefficient and a digital signal in advance and reading it out responsive to the inputted digital signal, in view of the point that filter characteristics of digital filters of an A/D converting unit and a D/A converting unit are equal one another, memories which are coefficient generating devices are used in common, and further, in view of the point :hat processing contents of respective digital filters are equal, a multiplier and an accumulator constituting the digital filter are used in common to reduce a circuit configuration considerably.

摘要翻译： A / DD / A转换装置，其中通过根据输入的数字信号预先存储滤波器系数和数字信号的相乘结果而省略乘法器，考虑到滤波器特性 A / D转换单元和D / A转换单元的数字滤波器彼此相等，作为系数产生装置的存储器是共同使用的，此外，考虑到各个数字滤波器的帽子处理内容相等 ，共同地使用构成数字滤波器的乘法器和累加器来显着地减少电路配置。

公开(公告)号：US20110103593A1

公开(公告)日：2011-05-05

申请号：US12613278

申请日：2009-11-05

申请人： Thirunathan Sutharsan

发明人： Thirunathan Sutharsan

IPC分类号： H04R5/00 ,  G10L21/00 ,  G06F17/00

CPC分类号： G06F3/162 ,  H03H17/04 ,  H03H17/0664 ,  H03H17/0671 ,  H03H2218/08 ,  H03H2218/085

摘要： Methods and systems for a pipelined dual audio path processing audio CODEC are disclosed and may comprise centrally generating multiplexer (MUX) select signals for clock domains in an audio CODEC including a plurality of audio inputs and audio processing paths. The MUX select signals may be generated in a single clock domain. Each of the audio processing paths may traverse a plurality of clock domains and may include infinite impulse response (IIR) and cascaded integrator comb (CIC) filters. One or more adders may be shared in the CIC filters, and one or more multipliers and one or more adders may be shared in the IIR filters. The clock domains may be synchronized utilizing the centrally generated enable signals. An output signal of the IIR filters may be buffered in each of the audio paths utilizing a first-in-first-out buffer. The MUX select signals may be generated utilizing a finite state machine.

摘要翻译： 公开了流水线式双音频路径处理音频CODEC的方法和系统，并且可以包括在包括多个音频输入和音频处理路径的音频编解码器中集中产生用于时钟域的多路复用器（MUX）选择信号。 MUX选择信号可以在单个时钟域中产生。 每个音频处理路径可以遍历多个时钟域，并且可以包括无限脉冲响应（IIR）和级联积分器梳（CIC）滤波器。 一个或多个加法器可以在CIC滤波器中共享，并且一个或多个乘法器和一个或多个加法器可以在IIR滤波器中共享。 可以使用集中产生的使能信号来同步时钟域。 IIR滤波器的输出信号可以利用先进先出缓冲器缓冲在每个音频路径中。 MUX选择信号可以利用有限状态机产生。