公开(公告)号：US20070287287A1

公开(公告)日：2007-12-13

申请号：US11759788

申请日：2007-06-07

申请人： Yun-Seung KANG ,  Jun SEO ,  Min-Chul CHAE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Woo-Jin CHO

发明人： Yun-Seung KANG ,  Jun SEO ,  Min-Chul CHAE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Woo-Jin CHO

IPC分类号： H01L21/44

CPC分类号： H01L27/11551 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/0688 ,  H01L27/11526

摘要： Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.

摘要翻译： 提供一种制造具有高纵横比的接触孔的半导体器件的方法。 该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

公开(公告)号：US20080124871A1

公开(公告)日：2008-05-29

申请号：US11773372

申请日：2007-07-03

申请人： Jun SEO ,  Jong-Heui SONG ,  Jae-Seung HWANG ,  Min-Chul CHAE ,  Woo-Jin CHO ,  Yun-Seung KANG ,  Young-Mi LEE

发明人： Jun SEO ,  Jong-Heui SONG ,  Jae-Seung HWANG ,  Min-Chul CHAE ,  Woo-Jin CHO ,  Yun-Seung KANG ,  Young-Mi LEE

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.

摘要翻译： 一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第 牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。 凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

公开(公告)号：US20090020816A1

公开(公告)日：2009-01-22

申请号：US12175364

申请日：2008-07-17

申请人： Woo-Jin CHO ,  Yong-Woo LEE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Min-Chul CHAE

发明人： Woo-Jin CHO ,  Yong-Woo LEE ,  Jae-Seung HWANG ,  Sung-Un KWON ,  Min-Chul CHAE

IPC分类号： H01L29/00

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： One embodiment generally described herein can be characterized as a semiconductor device. The semiconductor device can include a first transistor on a semiconductor substrate. A first interlayer insulating layer may be disposed over the first transistor and includes a first recess region. A single-crystalline semiconductor pattern may be disposed in the first recess region. A single-crystalline semiconductor plug may connect the semiconductor substrate to the single-crystalline semiconductor pattern. A second transistor may be disposed on the single-crystalline semiconductor pattern.

摘要翻译： 本文通常描述的一个实施例可以被表征为半导体器件。 半导体器件可以包括半导体衬底上的第一晶体管。 第一层间绝缘层可以设置在第一晶体管的上方，并且包括第一凹部区域。 单晶半导体图案可以设置在第一凹部区域中。 单晶半导体插头可以将半导体衬底连接到单晶半导体图案。 第二晶体管可以设置在单晶半导体图案上。