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公开(公告)号：US20060190772A1
公开(公告)日：2006-08-24
申请号：US11237655
申请日：2005-09-29
IPC分类号： G06F11/00
CPC分类号： H04L1/0082
摘要： A file control system of the present invention is a file control system performing DMA transfer and comprising a plurality of file control devices, each of which is provided between a host computer and an external storage device, a first file control device among the plurality of file control devices, checks the consistency between the data read from a memory and the first error detection code given in advance to the data, changes the error detection code added to the read data from the first error detection code to a second error detection code, when the inconsistency is detected by the check, changes at least a part of the data comprising the second error detection code and the data associated with the second error detection code, and executes DMA-transfer of the data which is changed or is not changed to a second file control device of the transfer destination.
摘要翻译： 本发明的文件控制系统是执行DMA传输的文件控制系统，包括多个文件控制装置，每个文件控制装置设置在主计算机和外部存储装置之间，多个文件中的第一文件控制装置 控制装置检查从存储器读取的数据与预先给出的数据之间的第一错误检测码的一致性，将从第一错误检测码添加到读取数据的错误检测码改变为第二错误检测码，当 通过检查检测到不一致，改变包括第二错误检测码的数据的至少一部分和与第二错误检测码相关联的数据，并且执行被改变或不被改变的数据的DMA传送 传送目的地的第二文件控制装置。
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公开(公告)号：US07624324B2
公开(公告)日：2009-11-24
申请号：US11237655
申请日：2005-09-29
IPC分类号： G06F11/00
CPC分类号： H04L1/0082
摘要： A file control system performing DMA (direct memory access) transfer is provided. The file control system includes file control devices, and each of the file control devices is provided between a host computer and an external storage device. A first file control device among the file control devices checks for errors in the data read from a memory, changes the error detection code added to the read data from a first error detection code to a second error detection code, changes at least a part of the data when an error is detected, and executes DMA-transfer of the data, which is changed or is not changed, to a second file control device of the transfer destination.
摘要翻译： 提供执行DMA（直接存储器访问）传送的文件控制系统。 文件控制系统包括文件控制装置，并且每个文件控制装置设置在主计算机和外部存储装置之间。 文件控制装置中的第一文件控制装置检查从存储器读取的数据中的错误，将从第一错误检测码添加到读取数据的错误检测码改变为第二错误检测码，改变至少一部分 当检测到错误时的数据，并且将改变或不改变的数据的DMA传送执行到传送目的地的第二文件控制装置。
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3.发明申请Method of controlling information processing system, information processing system, direct memory access control device and program 有权控制信息处理系统，信息处理系统，直接存储器访问控制装置和程序的方法公开(公告)号：US20060159115A1
公开(公告)日：2006-07-20
申请号：US11237767
申请日：2005-09-29
CPC分类号： G06F11/0793 , G06F11/0745 , H04L49/3009 , H04L49/602
摘要： In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.
摘要翻译： 在控制信息处理系统的方法中，其中信息处理设备连接到设置在路由设备中并具有第一属性或第二属性的多个输入/输出端口中的每一个，用于在信息处理之间进行数据传输 通过路由设备的设备，使所有信息处理设备停止数据传输的步骤，具有除了具有第一属性的输入/输出端口之外的第二特性的输入/输出端口的属性重置和识别信息的步骤 在路由装置中不能使用，并且在执行了识别信息的复位之后使信息处理装置重启数据传输的步骤。
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4.发明授权Method of controlling information processing system, information processing system, direct memory access control device and program 有权控制信息处理系统，信息处理系统，直接存储器访问控制装置和程序的方法公开(公告)号：US08032793B2
公开(公告)日：2011-10-04
申请号：US11237767
申请日：2005-09-29
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745 , H04L49/3009 , H04L49/602
摘要： In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.
摘要翻译： 在控制信息处理系统的方法中，其中信息处理设备连接到设置在路由设备中并具有第一属性或第二属性的多个输入/输出端口中的每一个，用于在信息处理之间进行数据传输 通过路由设备的设备，使所有信息处理设备停止数据传输的步骤，具有除了具有第一属性的输入/输出端口之外的第二特性的输入/输出端口的属性重置和识别信息的步骤 在路由装置中不能使用，并且在执行了识别信息的复位之后使信息处理装置重启数据传输的步骤。
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公开(公告)号：US07640374B2
公开(公告)日：2009-12-29
申请号：US11196469
申请日：2005-08-04
CPC分类号： G06F13/28
摘要： A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.
摘要翻译： 从存储器读取对应于描述符的数据的DMA装置以及描述符管理装置中的分割单元将一个描述符分成多个子描述符。 多个DMA控制器产生用于从存储器读取对应于多个子描述符的数据的多个读取请求。 存储器控制器根据多个读取请求从存储器读取相应的数据。
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公开(公告)号：US20060161694A1
公开(公告)日：2006-07-20
申请号：US11196469
申请日：2005-08-04
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.
摘要翻译： 从存储器读取对应于描述符的数据的DMA装置以及描述符管理装置中的分割单元将一个描述符分成多个子描述符。 多个DMA控制器产生用于从存储器读取对应于多个子描述符的数据的多个读取请求。 存储器控制器根据多个读取请求从存储器读取相应的数据。
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公开(公告)号：US20070073960A1
公开(公告)日：2007-03-29
申请号：US11604361
申请日：2006-11-27
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.
摘要翻译： 为了在PCI-Express通信系统的PCI-Express交换机中替换总线ID /设备ID之后能够将响应分组发送到原始请求节点，用于指示每个节点的唯一节点ID被设置到节点 。 此外，确认在一系列分组传送中分组是否以正确的顺序传送。 为此，在数据传送分组的地址字段中设置表示一系列分组传送中的分组的序列号的序列号。
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公开(公告)号：US07765357B2
公开(公告)日：2010-07-27
申请号：US11604361
申请日：2006-11-27
IPC分类号： G06F13/00 , G06F13/36 , G06F15/173
CPC分类号： G06F13/4022
摘要： To be able to transmit a response packet to the original request node after a bus ID/a device ID is replaced in the PCI-Express switch for a PCI-Express communication system, a unique node ID for indicating each node is set to the nodes. Additionally, it is confirmed whether or not the packet is transferred in the correct order in a series of packet transfers. For that purpose, a sequence code indicating the sequence number of a packet in a series of packet transfer is set in an address field of a packet of data transfer.
摘要翻译： 为了在PCI-Express通信系统的PCI-Express交换机中替换总线ID /设备ID之后能够将响应分组发送到原始请求节点，用于指示每个节点的唯一节点ID被设置到节点 。 此外，确认在一系列分组传送中分组是否以正确的顺序传送。 为此，在数据传送分组的地址字段中设置表示一系列分组传送中的分组的序列号的序列号。
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9.发明申请公开(公告)号：US20080104341A1
公开(公告)日：2008-05-01
申请号：US11905373
申请日：2007-09-28
IPC分类号： G06F12/00
CPC分类号： G06F13/28
摘要： In response to a request from a central processing unit (CPU) 11 (i.e., firmware) of a node 10, a transfer control unit 14a of a direct memory access (DMA) controller 14 transmits a message and data to another discretionary node 3 by way of a serial bus 1, a switch 2 or the like. In this event, the firmware stores data to be transmitted, a message, and a descriptor thereof in memory 12. In the case of requesting the transmission of the message, the descriptor contains a flag indicating “whether or not there is a need to wait for a response from the data transmission destination”. If the flag is set to ON, the transfer control unit 14a notifies the firmware of a simulated completion immediately instead of waiting for a completion response from the transmission destination node 3.
摘要翻译： 响应于来自节点10的中央处理单元（CPU）11（即固件）的请求，直接存储器访问（DMA）控制器14的传送控制单元14a将消息和数据发送到另一个可选节点3 通过串行总线1，开关2等。 在这种情况下，固件将要发送的数据，消息及其描述符存储在存储器12中。 在请求发送消息的情况下，描述符包含指示“是否需要等待来自数据发送目的地的响应”的标志。 如果标志设置为ON，则传送控制单元14a立即通知固件仿真完成，而不是等待来自发送目的地节点3的完成响应。
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10.发明授权公开(公告)号：US07849235B2
公开(公告)日：2010-12-07
申请号：US11905373
申请日：2007-09-28
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In response to a request from a central processing unit (CPU) 11 (i.e., firmware) of a node 10, a transfer control unit 14a of a direct memory access (DMA) controller 14 transmits a message and data to another discretionary node 3 by way of a serial bus 1, a switch 2 or the like. In this event, the firmware stores data to be transmitted, a message, and a descriptor thereof in memory 12. In the case of requesting the transmission of the message, the descriptor contains a flag indicating “whether or not there is a need to wait for a response from the data transmission destination”. If the flag is set to ON, the transfer control unit 14a notifies the firmware of a simulated completion immediately instead of waiting for a completion response from the transmission destination node 3.
摘要翻译： 响应于来自节点10的中央处理单元（CPU）11（即固件）的请求，直接存储器访问（DMA）控制器14的传送控制单元14a将消息和数据传送到另一个自由裁量节点3 串行总线1的方式，开关2等。 在这种情况下，固件将要发送的数据，消息及其描述符存储在存储器12中。在请求发送消息的情况下，描述符包含指示“是否需要等待 用于来自数据发送目的地的响应“。 如果标志设置为ON，则传送控制单元14a立即通知固件仿真完成，而不是等待来自发送目的地节点3的完成响应。
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