公开(公告)号：US11750200B2

公开(公告)日：2023-09-05

申请号：US17624063

申请日：2020-06-19

Applicant: ZTE Corporation

Inventor： Jun Liu ,  Zhaobi Wei ,  Shan Wang ,  Pei Duan ,  Mengbi Lei

IPC: H03L7/081 ,  H03L7/08 ,  H03L7/10 ,  H03L1/02

CPC classification number: H03L7/081 ,  H03L1/02 ,  H03L7/0802 ,  H03L7/10

Abstract: Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

公开(公告)号：US11700108B2

公开(公告)日：2023-07-11

申请号：US17625207

申请日：2020-07-06

Applicant: ZTE Corporation

Inventor： Jun Liu ,  Zhaobi Wei ,  Shan Wang ,  Mengbi Lei ,  Guojun Zhang

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC classification number: H04L7/0037

Abstract: Provided are a phase detection method and apparatus for a clock signal, and a communication device. A clock signal of a clock to be detected is sampled according to sampling periods set by a sampling clock; a phase angle value corresponding to a sampled clock signal in a current sampling period is obtained according to a mapping relationship between sampled signals and phase angle values; a phase difference corresponding to the current sampling period is subtracted from the phase angle value to obtain an initial phase value of the clock to be detected in the current sampling period, wherein the phase difference is a phase difference between the clock to be detected and the sampling clock in the current sampling period; and after the sampling ends, a final phase value of the clock to be detected is obtained according to initial phase values obtained in respective sampling periods.