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    Routing architecture for a programmable logic device
    1.
    发明授权
    Routing architecture for a programmable logic device 失效
    可编程逻辑器件的路由架构

    公开(公告)号：US06970014B1

    公开(公告)日：2005-11-29

    申请号：US10623709

    申请日：2003-07-21

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.

    摘要翻译： 本发明的实施例涉及在可编程逻辑器件（“PLD”）内互连诸如逻辑阵列块（“LAB”）的功能块的3边路由架构。 在三面路由架构中，功能块第一侧的输入和输出连接到第一通道，功能块第二侧上的输入和输出连接到第二通道，其中第二侧与第一通道相反 侧。 功能块第三侧的输入和输出连接到第三个通道。 与功能块的第四侧相关联的与第三侧相反的第四侧的第四通道仅耦合到第一通道和第二通道。 在一种配置中，第一侧，第二侧和第三侧中的每一个上的输入和输出具有相等数量的输入和输出。 在该配置中，第一通道，第二通道和第三通道中的每一个具有相同的宽度。 在另一种构造中，第一侧，第二侧或第三侧中的一个上的引脚数目与另一侧上的引脚数不同。

    Routing architecture for a programmable logic device
    2.
    发明授权
    Routing architecture for a programmable logic device 有权

    公开(公告)号：US06630842B1

    公开(公告)日：2003-10-07

    申请号：US10140287

    申请日：2002-05-06

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736

    摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides. In this configuration, the width of one of the first channel, the second channel, or the third channel differs from the width of another one of those channels. Input multiplexers route signals from the wires of the channels to the inputs of the function block. Output multiplexers and drivers drive the outputs of the function block through the wires of the channels. By placing the input multiplexers and the output multiplexers in certain relative arrangements, the logical distance that an output signal from the function block can travel on a wire is increased and that signal can be looped back to itself. In addition, each of the inputs and the outputs of the function block can be connected to both horizontal and vertical channels, and an output of the function block can be directly connected to an input of an adjacent function block.

    System and method for optimizing routing lines in a programmable logic device
    3.
    发明授权
    System and method for optimizing routing lines in a programmable logic device 有权
    用于优化可编程逻辑器件中路由线路的系统和方法

    公开(公告)号：US06895570B2

    公开(公告)日：2005-05-17

    申请号：US10057232

    申请日：2002-01-25

    申请人： David M. Lewis ,  Vaughn Betz ,  Paul Leventis ,  Michael Chan ,  Cameron R. McClintock ,  Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Richard Cliff

    发明人： David M. Lewis ,  Vaughn Betz ,  Paul Leventis ,  Michael Chan ,  Cameron R. McClintock ,  Andy L. Lee ,  Christopher F. Lane ,  Srinivas T. Reddy ,  Richard Cliff

    IPC分类号： G06F17/50 ,  H01L21/82 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  G06F17/5054 ,  G06F17/5077

    摘要： An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire.A routing architecture is an array that includes rows and columns of function blocks. The columns of the array are connected with horizontal lines (“H-line”) and the rows of the array are connected with vertical lines (“V-line). The types of H-lines include a H4 line that spans four function blocks, a H8 line that spans eight function blocks, and a H24 line that spans twenty-four function blocks. The types of V-lines include a V4 line that spans four function blocks, a V8 line that spans eight function blocks, and a V16 line that spans sixteen function blocks.

    摘要翻译： 本发明的实施例涉及将可编程逻辑器件（“PLD”）内的多个功能块互连的导线。 确定电线最佳物理长度。 具有最佳物理长度的导线尽可能快地将信号沿导线传送。 在PLD中使用的一些电线具有与电最佳物理长度基本相同的物理长度或电学最佳物理长度的调整以考虑非电学考虑。 如本文所使用的物理长度是测量的线的长度。 如本文所使用的，线的逻辑长度是导线跨越的功能块的数量。 假设功能块具有不同的高度和宽度，则线的逻辑长度根据线的方向而变化。 路由架构是包括功能块的行和列的数组。 数组的列与水平线（“H-line”）连接，阵列与垂直线（“V线”）连接，H线的类型包括四条功能块的H4线 ，一个跨越八个功能块的H8线，以及跨越二十四个功能块的H24线，V线的类型包括跨越四个功能块的V4线，跨越八个功能块的V8线，以及V16线 线跨越十六个功能块。

    Versatile logic element and logic array block
    4.
    发明授权
    Versatile logic element and logic array block 有权

    公开(公告)号：US06937064B1

    公开(公告)日：2005-08-30

    申请号：US10280723

    申请日：2002-10-24

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

    Versatile logic element and logic array block
    5.
    发明授权
    Versatile logic element and logic array block 有权

    公开(公告)号：US07432734B2

    公开(公告)日：2008-10-07

    申请号：US11743625

    申请日：2007-05-02

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

    Versatile logic element and logic array block
    6.
    发明授权
    Versatile logic element and logic array block 失效

    公开(公告)号：US07671626B1

    公开(公告)日：2010-03-02

    申请号：US12202053

    申请日：2008-08-29

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/177

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

    Versatile logic element and logic array block
    7.
    发明授权
    Versatile logic element and logic array block 有权

    公开(公告)号：US07218133B2

    公开(公告)日：2007-05-15

    申请号：US11050111

    申请日：2005-02-02

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Timothy Betz

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher F. Lane ,  Alexander Marquardt ,  Vikram Santurkar ,  Vaughn Timothy Betz

    IPC分类号： H03K19/003

    CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.