公开(公告)号：US06351485B1

公开(公告)日：2002-02-26

申请号：US09149770

申请日：1998-09-08

申请人： Zaw M. Soe ,  Ewunnet Gebre-Selassie ,  Mingde Pan

发明人： Zaw M. Soe ,  Ewunnet Gebre-Selassie ,  Mingde Pan

IPC分类号： H04B169

CPC分类号： H03L7/095 ,  H03B23/00 ,  H03L7/0891 ,  H03L7/197 ,  H04B1/69

摘要： A spread spectrum modulation technique uses digital control logic to switch back and forth between two feedback divider ratios so that the PLL spreads output clock frequency between two limits determined by the ratios. The spread spectrum control logic can be integrated into any PLL frequency synthesizer.

摘要翻译： 扩频调制技术使用数字控制逻辑在两个反馈分频比之间来回切换，使得PLL将输出时钟频率扩展到由比率确定的两个极限之间。 扩频控制逻辑可以集成到任何PLL频率合成器中。

公开(公告)号：US20140015578A1

公开(公告)日：2014-01-16

申请号：US14007538

申请日：2011-09-30

申请人： Ewunnet Gebre-Selassie ,  Dawson W. Kesling ,  Steven J. Kirch ,  Rahul D. Limaye ,  Shah M. Musa ,  Fugao Wang

发明人： Ewunnet Gebre-Selassie ,  Dawson W. Kesling ,  Steven J. Kirch ,  Rahul D. Limaye ,  Shah M. Musa ,  Fugao Wang

IPC分类号： H03L7/08

CPC分类号： H03L7/08 ,  H03L7/06 ,  H04B1/7085

摘要： A terminal includes control logic to control a phase-locked loop to output a spread-spectrum clocking signal. The control logic controls the generation of the spread-spectrum clocking signal by adjusting at least one parameter of the phase-locked loop. The parameter may be a charge pump setting or a loop-filter capacitance of the phase-locked loop, or their digital equivalents. Adjustment of the parameter reduces a predetermined portion of a communications spectrum. The predetermined portion may be located within a range of frequencies allocated to a specific channel, and reduction of the spectrum in this range may serve to reduce noise associated with clocking harmonics.

摘要翻译： 终端包括控制逻辑以控制锁相环以输出扩频时钟信号。 控制逻辑通过调节锁相环的至少一个参数来控制扩频时钟信号的产生。 该参数可以是电荷泵设置或锁相环路的环路滤波器电容或其数字等效电路。 该参数的调整减少通信频谱的预定部分。 预定部分可以位于分配给特定信道的频率的范围内，并且在该范围内的频谱的减小可以用于减少与时钟谐波相关联的噪声。

公开(公告)号：US08988122B2

公开(公告)日：2015-03-24

申请号：US14007538

申请日：2011-09-30

申请人： Ewunnet Gebre-Selassie ,  Dawson W. Kesling ,  Steven J. Kirch ,  Rahul D. Limaye ,  Shah M. Musa ,  Fugao Wang

发明人： Ewunnet Gebre-Selassie ,  Dawson W. Kesling ,  Steven J. Kirch ,  Rahul D. Limaye ,  Shah M. Musa ,  Fugao Wang

IPC分类号： H03L7/06 ,  H03L7/08 ,  H04B1/7085

CPC分类号： H03L7/08 ,  H03L7/06 ,  H04B1/7085

摘要： A terminal includes control logic to control a phase-locked loop to output a spread-spectrum clocking signal. The control logic controls the generation of the spread-spectrum clocking signal by adjusting at least one parameter of the phase-locked loop. The parameter may be a charge pump setting or a loop-filter capacitance of the phase-locked loop, or their digital equivalents. Adjustment of the parameter reduces a predetermined portion of a communications spectrum. The predetermined portion may be located within a range of frequencies allocated to a specific channel, and reduction of the spectrum in this range may serve to reduce noise associated with clocking harmonics.

摘要翻译： 终端包括控制逻辑以控制锁相环以输出扩频时钟信号。 控制逻辑通过调节锁相环的至少一个参数来控制扩频时钟信号的产生。 该参数可以是电荷泵设置或锁相环路的环路滤波器电容或其数字等效电路。 该参数的调整减少通信频谱的预定部分。 预定部分可以位于分配给特定信道的频率的范围内，并且在该范围内的频谱的减小可以用于减少与时钟谐波相关联的噪声。