公开(公告)号：US20070088965A1

公开(公告)日：2007-04-19

申请号：US11637064

申请日：2006-12-12

申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

IPC分类号： G06F1/00

CPC分类号： G06F1/3228 ,  G06F1/3203

摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

公开(公告)号：US07167989B2

公开(公告)日：2007-01-23

申请号：US10682892

申请日：2003-10-14

申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

IPC分类号： G06F9/00

CPC分类号： G06F1/3228 ,  G06F1/3203

摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

摘要翻译： 可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下运行，后者 用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。 基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。

公开(公告)号：US20050081067A1

公开(公告)日：2005-04-14

申请号：US10682892

申请日：2003-10-14

申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3228 ,  G06F1/3203

摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

摘要翻译： 可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下工作，后者 用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。 基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。