公开(公告)号：US07111186B2

公开(公告)日：2006-09-19

申请号：US10425213

申请日：2003-04-28

申请人： Zhigang Han ,  Cong Khieu ,  Kailashnath Nagarakanti

发明人： Zhigang Han ,  Cong Khieu ,  Kailashnath Nagarakanti

IPC分类号： G06F1/12

CPC分类号： G06F1/10

摘要： A CPU clock signal generated from a phase lock loop (PLL) circuit and a feedback signal of the PLL circuit are used in generating a JBUS clock signal. The CPU clock signal and the feedback signal include the same amount of static phase offset introduced by the PLL circuit. The CPU clock signal and the feedback signal are input to an alignment detection circuit and used in generating the JBUS clock signal. In one embodiment, the JBUS clock signal is generated in synchronization with the CPU clock signal and having the frequency of the feedback signal. The present invention reduces or eliminates misalignment of the leading edge of the JBUS signal with reference to a specific leading edge of the CPU clock signal due to the presence of static phase offset introduced by the PLL circuit.

摘要翻译： 使用从锁相环（PLL）电路产生的CPU时钟信号和PLL电路的反馈信号来产生JBUS时钟信号。 CPU时钟信号和反馈信号包括由PLL电路引入的相同量的静态相位偏移。 CPU时钟信号和反馈信号输入到对准检测电路，用于产生JBUS时钟信号。 在一个实施例中，JBUS时钟信号与CPU时钟信号同步产生并具有反馈信号的频率。 参考由PLL电路引入的静态相位偏移的存在，参考CPU时钟信号的特定前沿，本发明减小或消除了JBUS信号前沿的未对准。

公开(公告)号：US20070247251A1

公开(公告)日：2007-10-25

申请号：US11411186

申请日：2006-04-25

申请人： Kailashnath Nagarakanti ,  Kiritkumar Panchal ,  Sung-Hun Oh

发明人： Kailashnath Nagarakanti ,  Kiritkumar Panchal ,  Sung-Hun Oh

IPC分类号： H03L7/099

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/099

摘要： A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.

摘要翻译： 时钟电路。 时钟电路包括相位检测器和输出单元。 相位检测器被耦合以接收参考时钟信号和输出时钟信号，并且被配置为提供指示参考和输出时钟信号之间的相位差的相位信号。 输出单元被配置为提供输出时钟信号，并且耦合到第一电源电压节点和第二电源电压节点。 输出单元包括偏置电路和电压控制元件。 偏置电路被耦合以基于相位信号接收控制电压，并且被配置为基于接收到的控制电压产生偏置电压。 电压控制元件被配置为基于偏置电压来调整输出时钟信号的参数。 使用此配置可​​实现与电源无关的输出时钟。

公开(公告)号：US07242255B1

公开(公告)日：2007-07-10

申请号：US11120914

申请日：2005-05-02

申请人： Yen-Chung T. Chen ,  Kailashnath Nagarakanti ,  Sung-Hun Oh

发明人： Yen-Chung T. Chen ,  Kailashnath Nagarakanti ,  Sung-Hun Oh

IPC分类号： H03L7/00 ,  H03L7/08 ,  G05F3/02

CPC分类号： H03L7/0893

摘要： An apparatus that minimizes phase error and jitter in a phase-locked loop. The apparatus includes a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, which are coupled together to form a phase-locked loop. The charge pump within the phase-locked loop contains a pull-up network and a pull-down network which are coupled to each other, and a current compensation device. If the pull-up network and the pull-down network are both conducting, the current compensation device adjusts currents flowing through the pull-up network and through the pull-down network such that the currents are substantially equal. This ensures that very little current flows into the loop filter, thereby substantially minimizing a build-up of charge on a capacitor in the loop filter, which can cause phase error and jitter in the phase-locked loop.

摘要翻译： 一种使锁相环中的相位误差和抖动最小化的装置。 该装置包括耦合在一起以形成锁相环的相位/频率检测器，电荷泵，环路滤波器，压控振荡器和分频器。 锁相环内的电荷泵包括彼此耦合的上拉网络和下拉网络，以及电流补偿装置。 如果上拉网络和下拉网络都是导通的，则电流补偿装置调节流经上拉网络并通过下拉网络的电流，使得电流基本相等。 这确保了很少的电流流入环路滤波器，从而基本上最小化环路滤波器中的电容器上的电荷的累积，这可能导致锁相环中的相位误差和抖动。

公开(公告)号：US07372341B2

公开(公告)日：2008-05-13

申请号：US11411186

申请日：2006-04-25

申请人： Kailashnath Nagarakanti ,  Kiritkumar Panchal ,  Sung-Hun Oh

发明人： Kailashnath Nagarakanti ,  Kiritkumar Panchal ,  Sung-Hun Oh

IPC分类号： H03B1/00

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/099

摘要： A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.

摘要翻译： 时钟电路。 时钟电路包括相位检测器和输出单元。 相位检测器被耦合以接收参考时钟信号和输出时钟信号，并且被配置为提供指示参考和输出时钟信号之间的相位差的相位信号。 输出单元被配置为提供输出时钟信号，并且耦合到第一电源电压节点和第二电源电压节点。 输出单元包括偏置电路和电压控制元件。 偏置电路被耦合以基于相位信号接收控制电压，并且被配置为基于接收到的控制电压产生偏置电压。 电压控制元件被配置为基于偏置电压来调整输出时钟信号的参数。 使用此配置可​​实现与电源无关的输出时钟。