公开(公告)号：US20120119298A1

公开(公告)日：2012-05-17

申请号：US12944104

申请日：2010-11-11

申请人： Zhiqiang WU ,  Yi-Ming SHEU ,  Tsung-Hsing YU ,  Kuan-Lun CHENG ,  Chih-Pin TSAO ,  Wen-Yuan CHEN ,  Chun-Fu CHENG ,  Chih-Ching WANG

发明人： Zhiqiang WU ,  Yi-Ming SHEU ,  Tsung-Hsing YU ,  Kuan-Lun CHENG ,  Chih-Pin TSAO ,  Wen-Yuan CHEN ,  Chun-Fu CHENG ,  Chih-Ching WANG

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66575

摘要： A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°.

摘要翻译： 形成集成电路的方法包括：在衬底上形成沿着第一方向纵向布置的多个栅极结构。 对基板执行多个角度离子注入。 每个角度离子注入相对于第二方向具有相应的注入角度。 第二方向基本上平行于衬底的表面并且基本上与第一方向正交。 每个注入角度基本上大于0°。

公开(公告)号：US20130126981A1

公开(公告)日：2013-05-23

申请号：US13301873

申请日：2011-11-22

申请人： Jon-Hsu HO ,  Chih-Ching WANG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Chih-Chieh YEH ,  Ken-Ichi GOTO ,  Zhiqiang WU

发明人： Jon-Hsu HO ,  Chih-Ching WANG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Chih-Chieh YEH ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC分类号： H01L27/088

CPC分类号： H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

摘要： A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.