专利检索 ap:("Zhong Chen" OR "Shui-Qing Yu" OR "H. Alan Mantooth" OR "Andrea Wallace" OR "Syam Madhusoodhanan") AND inv:"Shui-Qing Yu" 第 1 页

1.

发明授权
High temperature optoelectronic devices for power electronics 有权

公开(公告)号：US11329209B1

公开(公告)日：2022-05-10

申请号：US16717065

申请日：2019-12-17

申请人： Zhong Chen , Shui-Qing Yu , H. Alan Mantooth , Andrea Wallace , Syam Madhusoodhanan

发明人： Zhong Chen , Shui-Qing Yu , H. Alan Mantooth , Andrea Wallace , Syam Madhusoodhanan

IPC分类号： H01L33/64 , H01L33/00

摘要： A high temperature optoelectronic isolator for power electronics operating above 250 degrees Celcius.

2.

发明申请
LATTICE MATCHED MULTI-JUNCTION PHOTOVOLTAIC AND OPTOELECTRONIC DEVICES 审中-公开
标题翻译： LATTICE MATCHED MULTI-JUNCTION光伏和光电器件

公开(公告)号：US20100301454A1

公开(公告)日：2010-12-02

申请号：US12743113

申请日：2008-11-10

申请人： Yong-Hang Zhang , Shade R. Johnson , Shui-Qing Yu , Ding Ding , Songnan Wu

发明人： Yong-Hang Zhang , Shade R. Johnson , Shui-Qing Yu , Ding Ding , Songnan Wu

IPC分类号： H01L29/22 , H01L29/20 , H01L21/20 , H01L21/36

CPC分类号： H01L31/0687 , Y02B10/10 , Y02E10/544

摘要： The present invention provides semiconductor structures comprising a substrate and at least three III-V and/or II-VI multi junction building blocks, each comprising a p-n junction having at least two alloy layers, formed over the substrate, provided at least one multi-junction building block comprises II-VI alloy layers. Further described are methods for preparing semiconductor structures utilizing a sacrificial or etch-stop ternary III-V alloy layer over an III-V substrate.

摘要翻译： 本发明提供了包括衬底和至少三个III-V和/或II-VI多结构建块的半导体结构，每个III-V和/或II-VI多结构建块包括形成在衬底上的具有至少两个合金层的pn结，结构构件包括II-VI合金层。进一步描述了利用在III-V衬底上的牺牲或蚀刻停止三元III-V合金层制备半导体结构的方法。