公开(公告)号：US06625560B1

公开(公告)日：2003-09-23

申请号：US09904783

申请日：2001-07-13

申请人： Ziaus S. Molla ,  Victor DaCosta ,  Seung Ho Hwang ,  Baegin Sung

发明人： Ziaus S. Molla ,  Victor DaCosta ,  Seung Ho Hwang ,  Baegin Sung

IPC分类号： G06F1100

CPC分类号： G01R31/31709 ,  G01R31/31922 ,  G01R31/31937

摘要： A method of testing a circuit having an interface which includes data and clock information where phase jitter is introduced into the clock that produces the clock information. The clock is cycled by increasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift advance in the clock. The clock is also cycled by decreasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift delay in the clock. The circuit under test is caused to sample the data using a clock derived from the clock information. The sampled data is then compared with reference data to determine the error rate.

摘要翻译： 一种测试具有接口的电路的方法，该接口包括将相位抖动引入产生时钟信息的时钟中的数据和时钟信息。 通过将时钟周期增加预定数量的时钟周期来循环时钟，以便在时钟中引入递增的相移提前。 时钟也通过在预定数量的时钟周期内减小时钟周期来循环，以便在时钟中引入增加的相移延迟。 使用由时钟信息导出的时钟对被测电路进行采样。 然后将采样数据与参考数据进行比较以确定错误率。