公开(公告)号：US07702925B2

公开(公告)日：2010-04-20

申请号：US11803051

申请日：2007-05-11

Applicant: J. Duane Northcutt ,  Seung Ho Hwang ,  James D. Lyle ,  James G. Hanko

Inventor： J. Duane Northcutt ,  Seung Ho Hwang ,  James D. Lyle ,  James G. Hanko

IPC: G06F21/00

CPC classification number: H04L25/03159 ,  H04L63/04 ,  H04L63/166 ,  H04L2025/03356 ,  H04L2025/03522

Abstract: In some embodiments, the invention is a personal digital network (“PDN”) including hardware (sometimes referred to as Ingress circuitry) configured to transcrypt encrypted content that enters the PDN. Typically, the transcryption (decryption followed by re-encryption) is performed in hardware within the Ingress circuitry and the re-encryption occurs before the decrypted content is accessible by hardware or software external to the Ingress circuitry. Typically, transcrypted content that leaves the Ingress circuitry remains in re-encrypted form within the PDN whenever it is transferred between integrated circuits or is otherwise easily accessible by software, until it is decrypted within hardware (sometimes referred to as Egress circuitry) for display or playback or output from the PDN. Typically, the PDN is implemented so that no secret in Ingress or Egress circuitry (for use or transfer by the Ingress or Egress circuitry) is accessible in unencrypted form to software or firmware within the PDN or to any entity external to the PDN. Other aspects of the invention are methods for protecting content in a PDN (e.g., an open computing system) and devices (e.g., multimedia graphics cards, set top boxes, or video processors) for use in a PDN.

Abstract translation: 在一些实施例中，本发明是一种个人数字网络（“PDN”），其包括配置成对进入PDN的加密内容进行加密的硬件（有时称为入口电路）。 通常，在入口电路内的硬件中执行转录（后续是重新加密的解密），并且在加密内容可以通过入口电路外部的硬件或软件访问之前发生重新加密。 通常，离开入口电路的加密内容在PDN之间保持重新加密的形式，无论其在集成电路之间传输还是由软件容易地访问，直到在硬件（有时称为出口电路）中被解密以进行显示或 从PDN播放或输出。 通常，PDN被实现为使得入口或出口电路（用于入口或出口电路的使用或传输）中的秘密可以以未加密的形式被访问到PDN内的软件或固件或PDN外部的任何实体。 本发明的其他方面是用于保护PDN（例如，开放式计算系统）中的内容和用于PDN中的设备（例如，多媒体图形卡，机顶盒或视频处理器）的方法。

公开(公告)号：US06870930B1

公开(公告)日：2005-03-22

申请号：US09579811

申请日：2000-05-26

Applicant: Gyudong Kim ,  Victor M. Da Costa ,  Bruce Kim ,  David D. Lee ,  Russel A. Martin ,  Seung Ho Hwang

Inventor： Gyudong Kim ,  Victor M. Da Costa ,  Bruce Kim ,  David D. Lee ,  Russel A. Martin ,  Seung Ho Hwang

IPC: H04L9/08 ,  H04L9/12 ,  H04L9/18 ,  H04N7/167 ,  H04N7/173 ,  H04L9/00 ,  H04K1/06

CPC classification number: G09G5/006 ,  H04L9/065 ,  H04L9/0844 ,  H04L9/12 ,  H04L2209/046 ,  H04L2209/34 ,  H04L2209/605 ,  H04N7/1675 ,  H04N7/17318 ,  H04N21/23476 ,  H04N21/44055 ,  H04N21/63345

Abstract: The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+1 bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link. Subsequent to step (e) and prior to step (f), the method can further include the step of encrypting the encoded n+2 bit control characters, such that the generating step generates a serial data stream in response to the encrypted data characters and the encrypted control characters.

Abstract translation: 本发明涉及用于在传输期间保护数字内容的系统和方法。 本发明的一个方案提供了一种用于在高速数字视频传输系统中进行加密的方法，该方法包括以下步骤：a）对n位数据字的第一序列进行转换控制编码，以编码到编码的n + 1位数据字符中，其中 n是正整数，b）用XOR掩码执行编码的n + 1位数据字符的异或掩蔽，以产生掩蔽的n + 1位数据字符; c）直流平衡屏蔽的n + 1位数据字符，以产生直流平衡，屏蔽的n + 2位数据字符; d）使用扰频公式对DC平衡掩蔽的n + 2位数据字符进行加扰，以产生加密的n + 2位数据字符; e）将控制数据编码为编码的n + 2位控制字符，f）响应于加密的数据字符和编码的控制字符产生串行数据流，以及g）通过通信链路发送串行数据流。 在步骤（e）之后和步骤（f）之后，该方法还可以包括对编码的n + 2位控制字符进行加密的步骤，使得生成步骤响应于加密的数据字符生成串行数据流，并且 加密的控制字符。

公开(公告)号：US06625560B1

公开(公告)日：2003-09-23

申请号：US09904783

申请日：2001-07-13

Applicant: Ziaus S. Molla ,  Victor DaCosta ,  Seung Ho Hwang ,  Baegin Sung

Inventor： Ziaus S. Molla ,  Victor DaCosta ,  Seung Ho Hwang ,  Baegin Sung

IPC: G06F1100

CPC classification number: G01R31/31709 ,  G01R31/31922 ,  G01R31/31937

Abstract: A method of testing a circuit having an interface which includes data and clock information where phase jitter is introduced into the clock that produces the clock information. The clock is cycled by increasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift advance in the clock. The clock is also cycled by decreasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift delay in the clock. The circuit under test is caused to sample the data using a clock derived from the clock information. The sampled data is then compared with reference data to determine the error rate.

Abstract translation: 一种测试具有接口的电路的方法，该接口包括将相位抖动引入产生时钟信息的时钟中的数据和时钟信息。 通过将时钟周期增加预定数量的时钟周期来循环时钟，以便在时钟中引入递增的相移提前。 时钟也通过在预定数量的时钟周期内减小时钟周期来循环，以便在时钟中引入增加的相移延迟。 使用由时钟信息导出的时钟对被测电路进行采样。 然后将采样数据与参考数据进行比较以确定错误率。

公开(公告)号：US08004375B2

公开(公告)日：2011-08-23

申请号：US12135363

申请日：2008-06-09

Applicant: Cheol-gyu Hwang ,  Sung-tae Choi ,  Jung-han Choi ,  Seung-ho Hwang ,  Young-hwan Kim ,  Dong-hyun Lee

Inventor： Cheol-gyu Hwang ,  Sung-tae Choi ,  Jung-han Choi ,  Seung-ho Hwang ,  Young-hwan Kim ,  Dong-hyun Lee

IPC: H01P1/203 ,  H01P7/08

CPC classification number: H01P1/2013 ,  H01P1/2005 ,  H01P11/008

Abstract: Provided is an Electromagnetic Bandgap (EBG) structure, particularly, a resonator and a bandpass filter having an overlay EBG structure, and a method of manufacturing the resonator. The resonator is manufactured by forming a transmission line and ground plates on a substrate, arranging a plurality of reflector units at regular intervals along the longitudinal direction of the transmission line, and removing at least one reflector among the plurality of reflectors, thus forming a common resonating mode. Therefore, since reflector units constructing capacitance components are separated from a substrate, it is possible to prevent electromagnetic waves from leaking out of the substrate and ensure a high Q characteristic in a high frequency environment due to a resonating unit formed between the reflector units.

Abstract translation: 提供了一种电磁带隙（EBG）结构，特别是具有覆盖EBG结构的谐振器和带通滤波器以及制造谐振器的方法。 谐振器通过在基板上形成传输线和接地板来制造，沿着传输线的纵向方向以规则的间隔布置多个反射器单元，并且去除多个反射器中的至少一个反射器，从而形成共同的 谐振模式。 因此，由于构成电容元件的反射器单元与基板分离，因此可以防止电磁波从基板泄漏出来，并且由于在反射器单元之间形成谐振单元，从而确保高频环境中的高Q特性。

公开(公告)号：US07589559B2

公开(公告)日：2009-09-15

申请号：US11643388

申请日：2006-12-20

Applicant: Daeyun Shim ,  Min-Kyu Kim ,  Gyudong Kim ,  Keewook Jung ,  Seung Ho Hwang

Inventor： Daeyun Shim ,  Min-Kyu Kim ,  Gyudong Kim ,  Keewook Jung ,  Seung Ho Hwang

IPC: H03K19/0175

CPC classification number: H04L5/20

Abstract: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。 在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。 第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片 包括用于检测共模电压变化的共模检测电路。 描述和要求保护其他实施例。

公开(公告)号：US07500032B2

公开(公告)日：2009-03-03

申请号：US11848758

申请日：2007-08-31

Applicant: Ook Kim ,  Eric Lee ,  Gyudong Kim ,  Zeehoon Jang ,  Baegin Sung ,  Nam Hoon Kim ,  Gijung Ahn ,  Seung Ho Hwang

Inventor： Ook Kim ,  Eric Lee ,  Gyudong Kim ,  Zeehoon Jang ,  Baegin Sung ,  Nam Hoon Kim ,  Gijung Ahn ,  Seung Ho Hwang

IPC: G06F13/38

CPC classification number: G06F13/385

Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.

Abstract translation: 包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。 电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体 （例如，用于传输到外部设备）。 本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。 电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对 歪斜等信息。 电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

公开(公告)号：US20080169838A1

公开(公告)日：2008-07-17

申请号：US11643388

申请日：2006-12-20

Applicant: Daeyun Shim ,  Min-Kyu Kim ,  Gyudong Kim ,  Keewook Jung ,  Seung Ho Hwang

Inventor： Daeyun Shim ,  Min-Kyu Kim ,  Gyudong Kim ,  Keewook Jung ,  Seung Ho Hwang

IPC: H01P5/00

CPC classification number: H04L5/20

Abstract: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。 在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。 第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片 包括用于检测共模电压变化的共模检测电路。 描述和要求保护其他实施例。

公开(公告)号：US07359437B2

公开(公告)日：2008-04-15

申请号：US10036234

申请日：2001-12-24

Applicant: Seung Ho Hwang ,  Jano Banks ,  Paul Daniel Wolf ,  Eric Lee ,  Baegin Sung ,  Albert M. Scalise

Inventor： Seung Ho Hwang ,  Jano Banks ,  Paul Daniel Wolf ,  Eric Lee ,  Baegin Sung ,  Albert M. Scalise

IPC: H04B1/66

CPC classification number: H04L1/0057 ,  G09G5/006 ,  H04L1/203 ,  H04L1/206 ,  H04L25/49 ,  H04N19/89

Abstract: A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., encoded video data and encoded auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, alternating bursts of encoded video data and encoded auxiliary data are transmitted over each of one or more channels of the link. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, and methods for sending encoded data over a serial link. In accordance with the invention, the data to be transmitted are encoded using a subset (sometimes referred to as a selected set of code words) of a full set of code words. The selected set of code words is selected such that each stream of encoded data (comprising only such code words) transmitted over a serial link has a bit pattern that is less susceptible to inter-symbol interference (“ISI”) during transmission than is the bit pattern determined by a conventionally encoded version of the same data (comprising not only the selected set of code words but also other members of the full set). In general, the best choice for the selected set of code words selected from a full set of binary code words depends on the particular coding implemented by the full set. Typically, the selected set of code words includes words whose serial patterns (during transmission) have fewer contiguous zeros and ones (and thus are less susceptible to ISI during transmission) than do those code words in the full set that are not selected. In preferred embodiments in which the bits of the selected set of code words are transmitted over a serial link as sequences of rising and falling voltage transitions, the bit pattern of each transmitted stream of the selected set of code words implements DC balancing to limit the voltage drift over time.

公开(公告)号：US07236553B1

公开(公告)日：2007-06-26

申请号：US10763905

申请日：2004-01-23

Applicant: Hoon Choi ,  Gyudong Kim ,  Daeyun Shim ,  Bruce Kim ,  Seung Ho Hwang

Inventor： Hoon Choi ,  Gyudong Kim ,  Daeyun Shim ,  Bruce Kim ,  Seung Ho Hwang

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H04L7/0008

Abstract: A data sampling method and circuit employing an oversampling clock to oversample a data signal, a phase tracker for use with or in a data sampling circuit, and a method for identifying a sequence of best sampling positions for sampling a data signal from signal samples generated using an oversampling clock. In some embodiments, data indicative of the phase of at least one of the oversampling clock's sampling positions relative to the center of the data eye are low-pass filtered in a manner determined by the data signal's bit rate. In other embodiments, the number of dead cycles of the phase tracker decision loop is reduced by generating possible solutions in parallel and moving the feedback point so as to occur as late as practical, or the phase tracker ignores a sample set when updating its determination of the best sampling position when the sample set indicates that the data signal has less than a predetermined number of transitions during a corresponding tracking period.

Abstract translation: 使用过采样时钟对数据信号进行过采样的数据采样方法和电路，与数据采样电路一起使用或在数据采样电路中使用的相位跟踪器，以及用于识别最佳采样位置序列的方法，用于从使用 过采样时钟。 在一些实施例中，指示相对于数据眼睛的中心的过采样时钟的采样位置中的至少一个的相位的数据以由数据信号的比特率确定的方式进行低通滤波。 在其他实施例中，相位跟踪器判定循环的死循环的数量通过并行产生可能的解并且将反馈点移动以便尽可能晚地发生而减少，或者当更新其样本集的确定时，相位跟踪器忽略样本集 当样本集合表示在对应的跟踪周期期间数据信号具有小于预定数量的转换时的最佳采样位置。

公开(公告)号：US06463092B1

公开(公告)日：2002-10-08

申请号：US09393235

申请日：1999-09-09

Applicant: Gyudong Kim ,  Min-Kyu Kim ,  Seung Ho Hwang

Inventor： Gyudong Kim ,  Min-Kyu Kim ,  Seung Ho Hwang

IPC: H04B138

CPC classification number: G09G5/006 ,  G09G5/008 ,  G09G2370/04 ,  H04L7/0008 ,  H04L25/4902

Abstract: The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.

Abstract translation: 该系统优选地包括在同一传输线上发送时钟和数据信号的唯一发射机。 接收机使用相同的传输线将数据信号发送回发射机。 发射机包括时钟发生器，解码器和线路接口。 时钟发生器产生包括可变位置下降沿的时钟信号。 下降沿位置被接收器解码以从时钟信号中提取数据。 接收机包括时钟再生器，数据解码器和返回通道编码器。 时钟再发生器监视传输线，接收信号，对它们进行滤波，并在接收机上根据传输线上的信号产生时钟信号。 返回通道编码器产生信号并在传输线上断言它们。 该信号被断言或叠加在发射机提供的时钟和数据信号上。