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公开(公告)号：US08917271B2
公开(公告)日：2014-12-23
申请号：US12897578
申请日：2010-10-04
申请人： Johnny S. Rhoades , Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Cynthia Ann Edgeworth Allison , Karl M. Wurstner , Karim M. Abdalla
发明人： Johnny S. Rhoades , Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Cynthia Ann Edgeworth Allison , Karl M. Wurstner , Karim M. Abdalla
CPC分类号： G06T15/005 , G06T17/20 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for per-vertex by multiple graphics pipelines. Geometric primitives that are generated in a first processing stage are collected and redistributed more evenly and in smaller batches to the multiple graphics pipelines for vertex processing in a second processing stage. The smaller batches do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second stage are balanced. Therefore, the performance of the tessellation and geometry shaders is improved.
摘要翻译： 本发明的一个实施例提出了一种用于通过多个图形管线重新分配由每个顶点由镶嵌和几何着色器生成的几何图元的技术。 在第一处理阶段中生成的几何图元在第二处理阶段被收集并且更均匀地并且以较小批次重新分布到多个图形流水线进行顶点处理。 较小的批次不超过图形管道的资源限制，并且第二阶段中图形管道的每顶点处理工作负载平衡。 因此，纹理和几何着色器的性能得到改善。
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公开(公告)号：US20110080404A1
公开(公告)日：2011-04-07
申请号：US12897578
申请日：2010-10-04
申请人： Johnny S. RHOADES , Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Cynthia Ann Edgeworth Allison , Karl M. Wurstner , Karim M. Abdalla
发明人： Johnny S. RHOADES , Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Cynthia Ann Edgeworth Allison , Karl M. Wurstner , Karim M. Abdalla
IPC分类号： G06T17/20
CPC分类号： G06T15/005 , G06T17/20 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for per-vertex by multiple graphics pipelines. Geometric primitives that are generated in a first processing stage are collected and redistributed more evenly and in smaller batches to the multiple graphics pipelines for vertex processing in a second processing stage. The smaller batches do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second stage are balanced. Therefore, the performance of the tessellation and geometry shaders is improved.
摘要翻译： 本发明的一个实施例提出了一种用于通过多个图形管线重新分配由每个顶点由镶嵌和几何着色器生成的几何图元的技术。 在第一处理阶段中生成的几何图元在第二处理阶段被收集并且更均匀地并且以较小批次重新分布到多个图形流水线进行顶点处理。 较小的批次不超过图形管道的资源限制，并且第二阶段中图形管道的每顶点处理工作负载平衡。 因此，纹理和几何着色器的性能得到改善。
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公开(公告)号：US20130038620A1
公开(公告)日：2013-02-14
申请号：US13208256
申请日：2011-08-11
申请人： Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Johnny S. Rhoades , Cynthia Ann Edgeworth Allison , Karim M. Abdalla
发明人： Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Johnny S. Rhoades , Cynthia Ann Edgeworth Allison , Karim M. Abdalla
CPC分类号： G06T1/20
摘要： One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle. The smaller tasks do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second cycle are balanced and make full use of resources. Therefore, the performance of the tessellation and geometry shaders is improved.
摘要翻译： 本发明的一个实施例提出了一种用于重新分配由镶嵌和几何着色器生成的几何图元以用于由多个图形管线进行处理的技术。 在第一个处理周期中生成的几何图元在第二个处理周期中被收集并且更均匀地并且在更小的任务中重新分布到用于顶点处理的多个图形流水线。 较小的任务不超过图形管道的资源限制，并且第二周期中的图形管道的每顶点处理工作负载平衡并充分利用资源。 因此，纹理和几何着色器的性能得到改善。
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公开(公告)号：US09436969B2
公开(公告)日：2016-09-06
申请号：US13208256
申请日：2011-08-11
申请人： Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Johnny S. Rhoades , Cynthia Ann Edgeworth Allison , Karim M. Abdalla
发明人： Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Johnny S. Rhoades , Cynthia Ann Edgeworth Allison , Karim M. Abdalla
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle. The smaller tasks do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second cycle are balanced and make full use of resources. Therefore, the performance of the tessellation and geometry shaders is improved.
摘要翻译： 本发明的一个实施例提出了一种用于重新分配由镶嵌和几何着色器生成的几何图元以用于由多个图形管线进行处理的技术。 在第一个处理周期中生成的几何图元在第二个处理周期中被收集并且更均匀地并且在更小的任务中重新分布到用于顶点处理的多个图形流水线。 较小的任务不超过图形管道的资源限制，并且第二周期中的图形管道的每顶点处理工作负载平衡并充分利用资源。 因此，纹理和几何着色器的性能得到改善。
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公开(公告)号：US07852340B2
公开(公告)日：2010-12-14
申请号：US11957358
申请日：2007-12-14
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J.M. Toksvig , Johnny S Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译： 公开了可扩展着色器架构。 根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。 着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。 着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。 着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。 着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。 每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。
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公开(公告)号：US07385607B2
公开(公告)日：2008-06-10
申请号：US10938042
申请日：2004-09-10
申请人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
发明人： Rui M. Bastos , Karim M. Abdalla , Christian Rouet , Michael J. M. Toksvig , Johnny S. Rhoades , Roger L. Allen , John Douglas Tynefield, Jr. , Emmett M. Kilgariff , Gary M. Tarolli , Brian Cabral , Craig Michael Wittenbrink , Sean J. Treichler
CPC分类号： G06T15/005
摘要： A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要翻译： 公开了可扩展着色器架构。 根据该架构，着色器包括多个着色器管线，每个着色器管线可以对光栅化像素数据执行处理操作。 着色器管线可以根据需要进行功能删除，从而防止着色器流水线造成芯片排斥。 着色器包括一个着色器分配器，用于处理光栅化的像素数据，然后有选择地将经处理的光栅化像素数据分配到各种着色器管道，有利于平衡工作负载。 着色器收集器将各种着色器管线的输出格式化为正确的顺序，以形成阴影像素数据。 着色器指令处理器（调度器）对各个着色器管线进行编程，以执行其预期任务。 每个着色器管道具有与着色器分配器和着色器指令处理器交互的着色器网守，使得通过着色器管线的像素数据被根据需要被控制和处理。
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公开(公告)号：US20120176377A1
公开(公告)日：2012-07-12
申请号：US13422498
申请日：2012-03-16
摘要： A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
摘要翻译： 根据本发明的一个实施例的组织用于存储纹理数据的存储器的方法包括访问纹理映射的mipmap级别的大小。 可以基于mipmap级别的大小来确定块维度。 存储器空间（例如，计算机可读介质）可以在逻辑上被划分为多个整数个可变维度的块。 块的尺寸以料滴为单位进行测量，每个料滴的固定尺寸为字节。 纹理映射的mipmap级别可以存储在存储器空间中。 所述mipmap级别的纹理坐标可以通过确定纹理坐标所驻留的料滴的料滴地址并确定特定料滴中的字节地址来转换为存储器空间的字节地址。
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公开(公告)号：US07218291B2
公开(公告)日：2007-05-15
申请号：US10940070
申请日：2004-09-13
CPC分类号： G06T11/40 , G06T15/005 , G06T15/50 , G06T15/80
摘要： A fragment processor includes a fragment shader distributor, a fragment shader collector, and a plurality of fragment shader pipelines. Each fragment shader pipeline executes a fragment shader program on a segment of fragments. The plurality of fragment shader pipelines operate in parallel, executing the same or different fragment shader programs. The fragment shader distributor receives a stream of fragments from a rasterization unit and dispatches a portion of the stream of fragments to a selected fragment shader pipeline until the capacity of the selected fragment shader pipeline is reached. The fragment shader distributor then selects another fragment shader pipeline. The capacity of each of the fragment shader pipelines is limited by several different resources. As the fragment shader distributor dispatches fragments, it tracks the remaining available resources of the selected fragment shader pipeline. A fragment shader collector retrieves processed fragments from the plurality of fragment shader pipelines.
摘要翻译： 片段处理器包括片段着色器分配器，片段着色器收集器和多个片段着色器管线。 每个片段着色器流水线在片段片段上执行片段着色器程序。 多个片段着色器管线并行操作，执行相同或不同的片段着色器程序。 片段着色器分配器从光栅化单元接收片段流，并将片段流的一部分分派到所选择的片段着色器管线，直到达到所选片段着色器管线的容量。 片段着色器分配器然后选择另一个片段着色器管道。 每个片段着色器管道的容量受到几个不同的资源的限制。 当片段着色器分配器调度片段时，它会跟踪所选片段着色器管道的剩余可用资源。 片段着色器收集器从多个片段着色器管道中检索已处理的片段。
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公开(公告)号：US08436868B2
公开(公告)日：2013-05-07
申请号：US13073020
申请日：2011-03-28
IPC分类号： G09G5/00
摘要： A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
摘要翻译： 根据本发明的一个实施例的组织用于存储纹理数据的存储器的方法包括访问纹理映射的mipmap级别的大小。 可以基于mipmap级别的大小来确定块维度。 存储器空间（例如，计算机可读介质）可以在逻辑上被划分为多个整数个可变维度的块。 块的尺寸以料滴为单位进行测量，每个料滴的固定尺寸为字节。 纹理映射的mipmap级别可以存储在存储器空间中。 所述mipmap级别的纹理坐标可以通过确定纹理坐标所驻留的料滴的料滴地址并确定特定料滴中的字节地址来转换为存储器空间的字节地址。
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公开(公告)号：US08456481B2
公开(公告)日：2013-06-04
申请号：US13422498
申请日：2012-03-16
IPC分类号： G06F12/00
摘要： A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
摘要翻译： 根据本发明的一个实施例的组织用于存储纹理数据的存储器的方法包括访问纹理映射的mipmap级别的大小。 可以基于mipmap级别的大小来确定块维度。 存储器空间（例如，计算机可读介质）可以在逻辑上被划分为多个整数个可变维度的块。 块的尺寸以料滴为单位进行测量，每个料滴的固定尺寸为字节。 纹理映射的mipmap级别可以存储在存储器空间中。 所述mipmap级别的纹理坐标可以通过确定纹理坐标所驻留的料滴的料滴地址并确定特定料滴中的字节地址来转换为存储器空间的字节地址。
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