公开(公告)号：US07178117B1

公开(公告)日：2007-02-13

申请号：US10821466

申请日：2004-04-08

申请人： Zunghang Yu ,  Ninh Ngo ,  Guy Dupenloup

发明人： Zunghang Yu ,  Ninh Ngo ,  Guy Dupenloup

IPC分类号： G06F17/50 ,  G06F9/45 ,  H03K17/693

CPC分类号： G06F17/5027

摘要： An RTL representation for a LAB is generated. A full chip RTL model is then generated using a plurality of the LAB RTLs. Using the full chip RTL model, a full chip simulation of the PLD chip is performed to verify and debug the electronic design.

摘要翻译： 生成LAB的RTL表示。 然后使用多个LAB RTL生成全芯片RTL模型。 使用全芯片RTL模型，执行PLD芯片的全芯片仿真以验证和调试电子设计。

公开(公告)号：US08336007B1

公开(公告)日：2012-12-18

申请号：US13343898

申请日：2012-01-05

申请人： Guy Dupenloup

发明人： Guy Dupenloup

IPC分类号： G06F17/50

CPC分类号： G06F7/53 ,  G06F2207/382

摘要： A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.

公开(公告)号：US06295636B1

公开(公告)日：2001-09-25

申请号：US09027283

申请日：1998-02-20

申请人： Guy Dupenloup

发明人： Guy Dupenloup

IPC分类号： G06F1710

CPC分类号： G06F17/5045

摘要： A method of generating synthesis scripts to synthesize integrated circuit (IC) designs in RTL level description into gate-level description comprising the steps of identifying hardware elements in the RTL code, determining key pins for each of said identified hardware elements, extracting design structure and hierarchy from the RTL code, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design and generating script to cause a logic synthesis tool to repeat said bottom-up and said top-down applications until certain predetermined constraints are satisfied.

摘要翻译： 一种产生合成脚本的方法，用于将RTL级别描述中的集成电路（IC）设计合成为门级描述，其包括以下步骤：识别RTL代码中的硬件元素，确定每个所述识别的硬件元件的关键引脚，提取设计结构和 从RTL代码生成层次结构，生成脚本，使逻辑综合工具将自下而上的综合应用于IC设计的模块和子模块，生成脚本，使逻辑综合工具将自上而下的特征应用于模块和子系统， IC设计和生成脚本的模块，使得逻辑综合工具重复所述自下而上和所述自上而下的应用，直到满足某些预定的约束。

公开(公告)号：US06289491B1

公开(公告)日：2001-09-11

申请号：US09027501

申请日：1998-02-20

申请人： Guy Dupenloup

发明人： Guy Dupenloup

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A method of determining circuit characteristics of an integrated circuit design as defined by a generic netlist comprising the steps of identifying hardware elements in the generic netlist, determining key characteristics for each of said identified hardware elements, determining interconnections of said identified hardware elements, and detecting the degree of conformity of said identified hardware elements, said key characteristics, and said interconnections to predetermined configurations. The systems further identifies all cells in the generic netlist, determines for each cell the type of cell, accumulates cell types and cell type counts, and notifies an operator of said accumulated values.

摘要翻译： 确定由通用网表定义的集成电路设计的电路特性的方法，包括以下步骤：识别通用网表中的硬件元件，确定每个所述识别的硬件元件的密钥特性，确定所述识别的硬件元件的互连，以及检测 所述识别的硬件元件的一致性，所述密钥特性和所述互连到预定配置。 系统进一步识别通用网表中的所有单元，确定每个单元格的单元格类型，累积单元格类型和单元格类型计数，并通知操作员所述累积值。

公开(公告)号：US06263483B1

公开(公告)日：2001-07-17

申请号：US09027512

申请日：1998-02-20

申请人： Guy Dupenloup

发明人： Guy Dupenloup

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A method of translating an integrated circuit chip (IC) design as represented by RTL code to generic netlist using a logic synthesis tool comprising the steps of parsing the RTL code using analyze command of the logic synthesis tool, building the generic netlist using evaluate command of the logic synthesis tool, and recording the generic netlist to a dump file outside the logic synthesis tool. The dump file comprises characteristics of each input ports of current design, characteristics of each output ports of the current design, and characteristics of each cells of the current design.

摘要翻译： 一种使用逻辑综合工具将由RTL代码表示的集成电路芯片（IC）设计转换为通用网表的方法，包括以下步骤：使用逻辑综合工具的分析命令解析RTL代码，使用评估命令 逻辑综合工具，并将通用网表记录在逻辑综合工具之外的转储文件中。 转储文件包括当前设计的每个输入端口的特征，当前设计的每个输出端口的特性以及当前设计的每个单元的特性。

公开(公告)号：US06836877B1

公开(公告)日：2004-12-28

申请号：US09026790

申请日：1998-02-20

申请人： Guy Dupenloup

发明人： Guy Dupenloup

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A method of generating synthesis scripts to synthesize integrated circuit (IC) designs described in a generic netlist into a gate-level description includes the steps of identifying hardware elements in a generic netlist, determining key pins for each of the identified hardware elements, extracting design structure and hierarchy from the generic netlist, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design, and generating script to cause a logic synthesis tool to repeat these bottom-up and top-down applications until constraints are satisfied.

摘要翻译： 一种生成合成脚本以将通用网表中描述的集成电路（IC）设计合成到门级描述中的方法包括以下步骤：识别通用网表中的硬件元件，确定每个所识别的硬件元件的关键引脚，提取设计 结构和层次结构，生成脚本，使逻辑综合工具将自下而上的综合应用于IC设计的模块和子模块，生成脚本，使逻辑综合工具将自上而下的特征应用于模块， IC设计的子模块，以及生成脚本，使逻辑综合工具重复这些自下而上和自上而下的应用，直到满足约束。

公开(公告)号：US06205572B1

公开(公告)日：2001-03-20

申请号：US09027399

申请日：1998-02-20

申请人： Guy Dupenloup

发明人： Guy Dupenloup

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method of determining circuit characteristics of buffering tree nets of an integrated circuit (IC) design comprising the steps of determining source pins of the nets of the buffering tree, determining fanout of each of said source pins, determining active edges and active levels of each of said source pins, and presenting said source pins, said fanout, and said active edge on a report.

摘要翻译： 一种确定集成电路（IC）设计的缓冲树网的电路特性的方法，包括以下步骤：确定缓冲树的网络的源引脚，确定每个所述源引脚的扇出，确定每个的所述源引脚的有效边沿和有效电平 的所述源极引脚，并且在报告上呈现所述源极引脚，所述扇出引脚和所述有效边沿。

公开(公告)号：US06173435B2

公开(公告)日：2001-01-09

申请号：US09027423

申请日：1998-02-20

申请人： Guy Dupenloup

发明人： Guy Dupenloup

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A method of synthesizing integrated circuit chip (IC) designs having clock signals defined internal to a module comprising the steps of mapping the IC design to a target technology with the internal clock defined, removing definitions of the internal clock, re-synthesizing the IC design, and re-defining the internal clock using new names of clock sources.

摘要翻译： 一种合成集成电路芯片（IC）设计的方法，其具有在模块内部定义的时钟信号，包括以下步骤：将IC设计映射到定义的内部时钟的目标技术，去除内部时钟的定义，重新合成IC设计 ，并使用新的时钟源名称重新定义内部时钟。

公开(公告)号：US07506017B1

公开(公告)日：2009-03-17

申请号：US10853427

申请日：2004-05-25

申请人： Guy Dupenloup

发明人： Guy Dupenloup

IPC分类号： G06F7/52

CPC分类号： G06F7/53 ,  G06F2207/382

摘要： A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.

摘要翻译： 提供可验证的双工乘法器电路。 在一种模式中，双工乘法器的电路用作N位×N位乘法器。 在另一种模式下，双工乘法器的电路用作双N / 2位×N / 2位乘法器。 因为相同的电路可以用作NxN乘法器和双N / 2xN / 2乘法器，所以集成电路资源是保守的。 双工乘法器电路使用可以使用逻辑综合工具自动合成的架构。 可以使用逻辑等效错误检查工具执行验证操作。 即使使用相对较大的双工乘法器（例如，N值为16以上的双工乘法器），也可以使用这种方法进行彻底的验证。

公开(公告)号：US07308659B1

公开(公告)日：2007-12-11

申请号：US10642084

申请日：2003-08-14

申请人： Gopinath Rangan ,  Guy Dupenloup ,  Wira Gunawan ,  Tzung-Chin Chang ,  Khai Nguyen

发明人： Gopinath Rangan ,  Guy Dupenloup ,  Wira Gunawan ,  Tzung-Chin Chang ,  Khai Nguyen

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are replaced by predetermined desired values corresponding to the floating values which are both stored in a lookup table. In another embodiment, when a floating value is detected, that value is ignored and the previous clock value is retained.

摘要翻译： 本发明旨在减少在对RTL中的寄存器建模时在三态和争用期间引入的浮置值造成的误差。 在一个实施例中，浮动值被对应于两者都存储在查找表中的浮动值的预定期望值替换。 在另一个实施例中，当检测到浮动值时，忽略该值并保留先前的时钟值。