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31 条记录 (耗时 0.014 秒)

    Self-compensating delay chain for multiple-date-rate interfaces
    3.
    发明授权
    Self-compensating delay chain for multiple-date-rate interfaces 有权
    多速率接口的自补偿延迟链

    公开(公告)号：US07200769B1

    公开(公告)日：2007-04-03

    申请号：US10037861

    申请日：2002-01-02

    申请人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    发明人： Yan Chong ,  Chiakang Sung ,  Bonnie I. Wang ,  Joseph Huang ,  Xiaobao Wang ,  Philip Pan ,  Tzung-Chin Chang

    IPC分类号： G06F1/04

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/108 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091

    摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

    摘要翻译： 用于延迟多数据速率接口的时钟信号的方法和装置。 一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。 还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。 第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。 第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

    On/off reference voltage switch for multiple I/O standards
    4.
    发明授权
    On/off reference voltage switch for multiple I/O standards 有权
    用于多个I / O标准的开/关参考电压开关

    公开(公告)号：US06911860B1

    公开(公告)日：2005-06-28

    申请号：US10037716

    申请日：2001-11-09

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Bonnie Wang ,  Philip Pan ,  Yan Chong ,  In Whan Kim ,  Gopinath Rangan ,  Tzung-Chin Chang

    IPC分类号： H03K17/35

    CPC分类号： H03K17/6871 ,  H03K3/356113 ,  H03K17/063

    摘要： A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.

    摘要翻译： 开关电路选择性地将某些I / O标准所需的参考电压提供给逻辑器件。 该电路接收与设备的I / O电源不同的专用电源。 其还可以包括电平移位电路，用于将具有由第一电源确定的逻辑电平的主控制信号转换成具有由专用电源确定的逻辑电平的第一控制信号。 开关电路还包括传输开关，其响应于至少第一控制信号将参考电压传递到输出。 传输开关可以是CMOS传输门，其中至少一个NMOS晶体管由第一控制信号控制，与由与第一控制信号互补的第二控制信号控制的至少一个PMOS晶体管并联。 第二控制信号可以由另一电平移位电路产生并具有由I / O电源确定的逻辑电平。

    Circuit for providing clock signals with low skew
    5.
    发明授权
    Circuit for providing clock signals with low skew 有权
    提供低偏移时钟信号的电路

    公开(公告)号：US06731142B1

    公开(公告)日：2004-05-04

    申请号：US10412705

    申请日：2003-04-10

    申请人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

    发明人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

    IPC分类号： H03K2100

    CPC分类号： H03M9/00 ,  G06F1/08 ,  H03K5/135

    摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

    摘要翻译： 公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。 时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。 在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。 移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。 来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。 延迟电路延迟输入参考时钟。 在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。 由于所有输出路径中的延迟相匹配，所以偏斜最小化。

    Circuit for providing clock signals with low skew
    7.
    发明授权
    Circuit for providing clock signals with low skew 有权
    提供低偏移时钟信号的电路

    公开(公告)号：US06549045B1

    公开(公告)日：2003-04-15

    申请号：US10043620

    申请日：2002-01-11

    申请人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

    发明人： Bonnie Wang ,  Chiakang Sung ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopi Rangan ,  Yan Chong ,  Phillip Pan ,  Tzung-Chin Chang

    IPC分类号： H03K2100

    CPC分类号： H03M9/00 ,  G06F1/08 ,  H03K5/135

    摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

    摘要翻译： 公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。 时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。 在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。 移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。 来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。 延迟电路延迟输入参考时钟。 在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。 由于所有输出路径中的延迟相匹配，所以偏斜最小化。

    Techniques for controlling on-chip termination resistance using voltage range detection
    8.
    发明授权
    Techniques for controlling on-chip termination resistance using voltage range detection 有权
    使用电压范围检测控制片上终端电阻的技术

    公开(公告)号：US07218155B1

    公开(公告)日：2007-05-15

    申请号：US11040343

    申请日：2005-01-20

    申请人： Tzung-Chin Chang ,  Xiaobao Wang ,  Henry Kim ,  Chiakang Sung ,  Khai Q. Nguyen ,  Bonnie Wang ,  Jeffrey Tyhach ,  Gopinath Rangan

    发明人： Tzung-Chin Chang ,  Xiaobao Wang ,  Henry Kim ,  Chiakang Sung ,  Khai Q. Nguyen ,  Bonnie Wang ,  Jeffrey Tyhach ,  Gopinath Rangan

    IPC分类号： H03B1/00

    CPC分类号： H03K19/0005

    摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.

    摘要翻译： 提供了使用校准电路控制输入或输出（IO）缓冲器中的片上终端电阻的技术。 校准电路监视外部电阻和片上晶体管组之间的电压。 当外部电阻和晶体管组之间的电压在选定范围内时，校准电路会使晶体管的有效电阻尽可能接近外部电阻的电阻。 校准电路使得IO缓冲器中的另一组晶体管能够使得IO缓冲器中的晶体管的有效导通电阻与外部电阻器的电阻紧密匹配。