公开(公告)号：US10311193B2

公开(公告)日：2019-06-04

申请号：US14823197

申请日：2015-08-11

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko Kalte ,  Lukas Funke

IPC: G06F17/50

Abstract: A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.

公开(公告)号：US09628085B1

公开(公告)日：2017-04-18

申请号：US15334659

申请日：2016-10-26

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko Kalte ,  Dominik Lubeley ,  Lukas Funke

IPC: G11C7/10 ,  H03K19/177 ,  G11C7/22

CPC classification number: H03K19/1776 ,  G11C7/10 ,  G11C7/222 ,  H03K19/17776

Abstract: A method for accessing signals of a programmable logic device having a functional level and a configuration level at run time when the programmable logic device is executing a predefined configuration. An access to at least one signal value that has a number of bits is requested. The individual bits in the configuration are each located in an address unit with one address offset apiece such that one or more bits of a signal value are located in one address unit. A bitwise access to the requested signal values takes place, wherein the accesses to the individual bits are sorted as a function of the address unit containing the applicable bit in such a manner that the accesses to all bits located in an address unit take place in sequence as a function of the address offset, independently of the signal containing the applicable bit.

公开(公告)号：US10318687B2

公开(公告)日：2019-06-11

申请号：US14753439

申请日：2015-06-29

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko Kalte ,  Lukas Funke

IPC: G06F7/60 ,  G06F17/10 ,  G06F17/50 ,  G06F8/30

Abstract: A method for generating FPGA code based on an FPGA model with at least one signal value that is modeled as a constant. A constant is inserted with a predefined signal value in the FPGA model. A switching variable is set in the FPGA model for switching between a normal mode and a calibration mode for the FPGA code. The FPGA code is generated for the FPGA model having the implementation of the constants in the FPGA code, wherein the implementation of the constants when the switching variable is set for normal mode includes the implementation of the constants as a fixed value in the FPGA code, and the implementation of the constants when the switching variable is set for calibration mode includes the implementation of the constants as a modifiable signal value in the FPGA code. A method for calibrating an FPGA model is also provided.

公开(公告)号：US10223077B2

公开(公告)日：2019-03-05

申请号：US14863494

申请日：2015-09-24

Applicant: dSPACE digital signal processing and control engineering GmbH

Inventor： Heiko Kalte ,  Lukas Funke

IPC: G06F17/50 ,  G06F8/35

Abstract: A method for automatically determining models signals of an FPGA program which are readable from the FPGA with the aid of a readback following an FPGA build, including the following steps: generating an FPGA model and generating an FPGA code from the FPGA model, the method comprising the additional step of an automatic analysis for the purpose of identifying signals which are readable from the FPGA with the aid of a readback, prior to the completion of the step of generating the FPGA code from the FPGA model, and the method comprises the step of outputting signals which are readable from the FPGA with the aid of a readback. A data processing device is also provided for carrying out the method.