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公开(公告)号:US20180349255A1
公开(公告)日:2018-12-06
申请号:US15996850
申请日:2018-06-04
Inventor: Matthias FROMME , Jochen SAUER , Matthias SCHMITZ
Abstract: A method and device for transmitting metrologically acquired and digitized measured data in a test device. The measured data corresponds to a program task, and a direction of the transmission of the measured data from a measured data transmitter of the test device is provided via a data channel to a measured data receiver of the test device. The measured data transmitter has a signal preprocessing processor, a task monitoring processor and a data channel arbiter. Via the task monitoring processor, a task ID data packet is generated at an execution start of the program task or at an execution end of the program task, and the task ID data packet is transmitted to the data channel arbiter. Via the data channel arbiter, the measured data and the task ID data packet are successively forwarded via the data channel as a data stream to the measuring data receiver.
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2.
公开(公告)号:US20180357186A1
公开(公告)日:2018-12-13
申请号:US15995711
申请日:2018-06-01
Inventor: Matthias FROMME , Jochen SAUER , Matthias SCHMITZ
CPC classification number: G06F13/126 , G06F9/44505 , G06F9/4843 , G06F13/102 , G06F13/4243 , G06F15/76 , G06F15/7867
Abstract: A number of software routines comprising at least two software routines are created for an interface unit of a computer system having a first and a second interface processor for forwarding input data from a peripheral to a processor of the computer system on which software is programmed. A first subset of the software routines is assigned to a first category provided for task-synchronous data transfer, and a second subset of the software routines are assigned to a second category provided for continuous data transfer. The first interface processor is programmed with the first subset and the second interface processor with the second subset of software routines. During execution of the software, the first subset is cyclically executed by the first interface processor at a first cycle rate, and the second subset is cyclically executed by the second interface processor at a second cycle rate.
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