公开(公告)号：US20250069901A1

公开(公告)日：2025-02-27

申请号：US18456446

申请日：2023-08-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tung Yao LIN ,  Yi Dao WANG

IPC: H01L21/48 ,  B23K1/00 ,  B23K1/005 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16

Abstract: A method for manufacturing a package structure is provided. The method includes providing a package structure including a first region and a second region different from the first region, wherein the package structure comprises a package substrate having an active surface and a backside surface; and irradiating the package structure by a first light beam along a first direction from the active surface toward the backside surface, wherein the first light beam only irradiates the first region without irradiating the second region.

公开(公告)号：US12228778B2

公开(公告)日：2025-02-18

申请号：US17866400

申请日：2022-07-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jr-Wei Lin ,  Mei-Ju Lu

IPC: G02B6/26 ,  G02B6/30 ,  G02B6/42 ,  B82Y20/00 ,  G02B6/10 ,  G02B6/12 ,  G02B6/122 ,  G02B6/36

Abstract: An optoelectronic package is provided. The optoelectronic package includes a photonic component, an optical component, and a connection element. The photonic component includes an optical transmission portion, which includes a plurality of first terminals exposed from a first surface of the photonic component. The optical component faces the first surface of the photonic component. The optical component is configured to transmit optical signals to or receive optical signals from the optical transmission portion. The connection element is disposed between the first surface of the photonic component and the optical component. The connection element is configured to reshape the optical signals.

公开(公告)号：US20250054877A1

公开(公告)日：2025-02-13

申请号：US18931026

申请日：2024-10-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan LEE ,  Chen-Chao WANG ,  Chang Chi LEE

IPC: H01L23/552 ,  H01L23/31 ,  H01L25/16

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.

公开(公告)号：US12224481B2

公开(公告)日：2025-02-11

申请号：US18118738

申请日：2023-03-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee ,  Chun Chen Chen ,  Yuanhao Yu

IPC: H01Q1/22 ,  H01L23/31 ,  H01L23/66 ,  H01Q1/40 ,  H01Q21/00 ,  H01Q21/06

Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.

公开(公告)号：US12206185B2

公开(公告)日：2025-01-21

申请号：US17503228

申请日：2021-10-15

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mark Gerber

IPC: H01Q1/22 ,  H01Q5/378 ,  H01Q23/00

Abstract: The present disclosure provides an antenna device. The antenna device includes a dielectric element including a first region and a second region, a first antenna disposed on the first region, and a second antenna disposed on the second region. The first antenna and the second antenna are configured to operate in different frequencies. The first antenna and the second antenna are misaligned in directions perpendicular and parallel to a surface of the dielectric element on which the first antenna or the second antenna is disposed.

公开(公告)号：US12183683B2

公开(公告)日：2024-12-31

申请号：US17501952

申请日：2021-10-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wei-Jen Wang ,  Po-Jen Cheng ,  Fu-Yuan Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.

公开(公告)号：US20240421086A1

公开(公告)日：2024-12-19

申请号：US18211222

申请日：2023-06-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Pao-Nan LEE ,  Syu-Tang LIU ,  Yu-Hsun CHANG

IPC: H01L23/528 ,  H01L25/065

Abstract: An electronic device is disclosed. The electronic device includes a first electronic component, a second electronic component, and a circuit structure. The circuit structure is supported by the first electronic component and the second electronic component. The circuit structure electrically connects the first electronic component to the second electronic component and is configured to provide the first electronic component and the second electronic component with a power.

公开(公告)号：US12165963B2

公开(公告)日：2024-12-10

申请号：US18375140

申请日：2023-09-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

公开(公告)号：US12136579B2

公开(公告)日：2024-11-05

申请号：US18226210

申请日：2023-07-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hsu-Nan Fang

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373

Abstract: A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

公开(公告)号：US20240355763A1

公开(公告)日：2024-10-24

申请号：US18761075

申请日：2024-07-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： En Hao HSU ,  Kuo Hwa TZENG ,  Chia-Pin CHEN ,  Chi Long TSAI

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/022 ,  H01L2224/02377 ,  H01L2224/13018

Abstract: An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.