公开(公告)号：US07750916B2

公开(公告)日：2010-07-06

申请号：US10499875

申请日：2002-12-20

申请人： Martin Whitaker

发明人： Martin Whitaker

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F9/3895 ,  G06F9/345

摘要： A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory address engine with the initializing parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.

摘要翻译： 描述了一种生成表示逻辑空间中的连续点的不连续的存储器地址流的方法。 该方法包括：生成描述逻辑空间中的连续点的初始化参数; 使用初始化参数配置内存地址引擎; 根据初始化参数在存储器地址引擎中执行算法以产生多个不连续的存储器地址; 以及将不连续的存储器地址对准到存储器地址流中以输出到数据存储器。 本发明特别适用于存在多个存储器地址引擎的SIMD处理技术。

公开(公告)号：US07174442B2

公开(公告)日：2007-02-06

申请号：US10432203

申请日：2001-11-21

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F12/00

CPC分类号： G06F9/30043 ,  G06F9/345 ,  G06F13/28

摘要： A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address vector from the non-sequential addresses, and using the address vector in a block fetch command to a data store.

摘要翻译： 描述了对诸如SIMD处理器之类的数据并行处理器执行数据提取操作的方法。 该操作具体涉及使用多个非顺序数据地址。 该方法包括从非顺序地址构建线性地址向量，并且使用块获取命令中的地址向量到数据存储。

公开(公告)号：US20050206649A1

公开(公告)日：2005-09-22

申请号：US10499875

申请日：2002-12-20

申请人： Martin Whitaker

发明人： Martin Whitaker

IPC分类号： A61B5/055 ,  A61B8/00 ,  G06F9/345 ,  G06F13/28 ,  G06F12/00

CPC分类号： G06F9/3895 ,  G06F9/345

摘要： A method of generating a stream non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initialising parameters describing the contiguous points in the logical space; configuring a memory address engine with the initialising parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.

摘要翻译： 描述了一种生成表示逻辑空间中的连续点的流不连续的存储器地址的方法。 该方法包括：生成描述逻辑空间中的连续点的初始化参数; 使用初始化参数配置内存地址引擎; 根据初始化参数在存储器地址引擎中执行算法以产生多个不连续的存储器地址; 以及将不连续的存储器地址对准到存储器地址流中以输出到数据存储器。 本发明特别适用于存在多个存储器地址引擎的SIMD处理技术。

公开(公告)号：US08046514B2

公开(公告)日：2011-10-25

申请号：US10432309

申请日：2001-11-21

申请人： Martin Whitaker

发明人： Martin Whitaker

IPC分类号： G06F13/372 ,  G06F13/00

CPC分类号： G06F13/4226

摘要： A system and method of broadcasting data to multiple targets across a system bus, such as the peripheral component interconnect (PCI) bus, that does not normally support broadcast transfers, in which one target responds to the bus transaction and the remaining targets listen in on the bus transaction to receive data from the system bus. The responding target stalls the bus transaction when any of the listening targets communicate to the responding target that they are temporarily unable to accept the data on the bus.

摘要翻译： 一种系统和方法，用于通过诸如外围部件互连（PCI）总线的系统总线向多个目标广播数据，这些总线通常不支持广播传输，其中一个目标响应于总线事务，其余目标收听 总线事务从系统总线接收数据。 当任何监听目标与响应目标通信时，响应目标会停止总线事务，使其暂时无法接受总线上的数据。

公开(公告)号：US07865662B2

公开(公告)日：2011-01-04

申请号：US10539493

申请日：2003-12-17

申请人： Ian Jalowiecki ,  Martin Whitaker ,  John Lancaster ,  Donald Boughton

发明人： Ian Jalowiecki ,  Martin Whitaker ,  John Lancaster ,  Donald Boughton

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F15/8038

摘要： An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described. The alternation network comprises: a plurality of alternation modules connected in series together, each module comprising: a plurality of cascaded logic gates arranged to propagate a match parity signal via the gates along at least part of a matching result vector, the matching result vector being generated by execution of a matching instruction on the content addressable memory, and the logic gates being configured to change the parity of the match parity signal in accordance with the matching result vector; and a vector output arranged to output a parity level vector of the propagated match parity signal present at the each gate of the plurality of logic gates; a logic network for dividing the matching result vector into an odd match vector and an even match vector representing respectively odd and even numbered elements of the matching result vector, by use of the parity level vector, and means for writing a selected one of the odd and even match vectors to the content addressable memory.

摘要翻译： 描述了用于实现分割和征服算法的内容可寻址存储器的交替网络。 所述交替网络包括：串联连接的多个交替模块，每个模块包括：多个级联逻辑门，布置成沿着匹配结果向量的至少一部分经由所述门传播匹配奇偶校验信号，所述匹配结果向量为 通过在内容可寻址存储器上执行匹配指令而产生，并且逻辑门被配置为根据匹配结果向量改变匹配奇偶校验信号的奇偶校验; 以及矢量输出，被布置为输出存在于所述多个逻辑门的每个门处的所传播的匹配奇偶校验信号的奇偶校验电平矢量; 用于通过使用奇偶校验电平矢量将匹配结果矢量划分为奇数匹配向量和偶数匹配向量，表示分别为奇数和偶数编号的匹配结果向量元素的偶数向量;以及用于写入奇数 甚至将向量匹配到内容可寻址存储器。

公开(公告)号：US07096318B2

公开(公告)日：2006-08-22

申请号：US10432307

申请日：2001-11-21

申请人： Ian Paul Jalowiecki ,  John Lancaster ,  Anargyros Krikelis

发明人： Ian Paul Jalowiecki ,  John Lancaster ,  Anargyros Krikelis

IPC分类号： G06F13/28

CPC分类号： G11C15/04 ,  G11C15/00

摘要： A compound associative memory for use with a data-parallel computer, and a method of storing/retrieving data in the compound associative memory is disclosed. The memory comprises a bit-parallel word-organized associative memory having an array of associative memory cells arranged to be capable of bit-parallel search and write operations. A bit-serial associative memory having an array of memory cells arranged to be capable of bit-serial search and write operations, but not word bit-parallel search and write operations, is also included. The bit-serial memory is operatively connected to the bit-parallel memory and arranged to operate as an extension of the same. The method comprises searching the bit-parallel word-organized associative memory and/or the bit-serial associative memory coupled to the bit-parallel memory for data matching search data, and marking the memory cells having stored data matching the search data.

摘要翻译： 公开了一种与数据并行计算机一起使用的复合关联存储器，以及在复合关联存储器中存储/检索数据的方法。 存储器包括位并行字组织的关联存储器，其具有布置成能够进行位并行搜索和写入操作的关联存储器单元的阵列。 还包括具有布置成能够进行位串行搜索和写入操作而不是字位并行搜索和写入操作的存储器单元阵列的位串行关联存储器。 位串行存储器可操作地连接到比特并行存储器并且被布置为作为其扩展来操作。 该方法包括搜索与并行存储器耦合的位并行字组织关联存储器和/或位串联相关存储器，用于搜索数据匹配，以及标记具有与搜索数据匹配的存储数据的存储器单元。