公开(公告)号：US07174442B2

公开(公告)日：2007-02-06

申请号：US10432203

申请日：2001-11-21

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F12/00

CPC分类号： G06F9/30043 ,  G06F9/345 ,  G06F13/28

摘要： A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address vector from the non-sequential addresses, and using the address vector in a block fetch command to a data store.

摘要翻译： 描述了对诸如SIMD处理器之类的数据并行处理器执行数据提取操作的方法。 该操作具体涉及使用多个非顺序数据地址。 该方法包括从非顺序地址构建线性地址向量，并且使用块获取命令中的地址向量到数据存储。

公开(公告)号：US09195467B2

公开(公告)日：2015-11-24

申请号：US12993793

申请日：2009-05-20

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F9/38 ,  G06F15/80

CPC分类号： G06F9/3887 ,  G06F9/3016 ,  G06F9/3889 ,  G06F9/3891 ,  G06F15/8007

摘要： Improvements Relating to Single Instruction Multiple Data (SIMD) Architectures A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks.

摘要翻译： 关于单指令多数据（SIMD）架构的改进描述了并行处理多个不同处理指令流的并行处理器。 处理器包括多个数据处理单元; 以及多个SIMD（单指令多数据）控制器，每个SIMD（单指令多数据）控制器可连接到多个数据处理单元的一组数据处理单元，并且每个SIMD控制器被布置成处理具有主动连接的数据处理单元的子组的单独处理任务 从数据处理单元组中选择。 并行处理器被布置为在接收到的处理指令流的控制下动态地改变每个SIMD控制器主动连接到的数据处理单元的子组的大小，从而允许每个SIMD控制器主动地连接到不同数量的处理单元 不同的处理任务。

公开(公告)号：US20110191567A1

公开(公告)日：2011-08-04

申请号：US12993793

申请日：2009-05-20

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F9/30

CPC分类号： G06F9/3887 ,  G06F9/3016 ,  G06F9/3889 ,  G06F9/3891 ,  G06F15/8007

摘要： Improvements Relating to Single Instruction Multiple Data (SIMD) Architectures A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks.

摘要翻译： 关于单指令多数据（SIMD）架构的改进描述了并行处理多个不同处理指令流的并行处理器。 处理器包括多个数据处理单元; 以及多个SIMD（单指令多数据）控制器，每个SIMD（单指令多数据）控制器可连接到多个数据处理单元的一组数据处理单元，并且每个SIMD控制器被布置成处理具有主动连接的数据处理单元的子组的单独处理任务 从数据处理单元组中选择。 并行处理器被布置为在接收到的处理指令流的控制下动态地改变每个SIMD控制器主动连接到的数据处理单元的子组的大小，从而允许每个SIMD控制器主动地连接到不同数量的处理单元 不同的处理任务。

公开(公告)号：US20110185151A1

公开(公告)日：2011-07-28

申请号：US12993801

申请日：2009-05-20

申请人： Martin Whitaker ,  John Lancaster

发明人： Martin Whitaker ,  John Lancaster

IPC分类号： G06F15/80 ,  G06F15/76 ,  G06F9/02

CPC分类号： G06F15/8015

摘要： A parallel processor is described which is operated in a SIMD manner. The processor comprises: a plurality of processing elements connected in a string and grouped into a plurality of processing units, wherein each processing unit comprises a plurality of processing elements which each have direct interconnections with all of the other processing elements within the respective processing unit, the interconnections enabling data transfer between any two elements within a unit to be effected in a single clock cycle.

摘要翻译： 描述了以SIMD方式操作的并行处理器。 处理器包括：串联连接并分组成多个处理单元的多个处理元件，其中每个处理单元包括多个处理元件，每个处理元件与相应处理单元内的所有其它处理元件具有直接互连， 能够在单个时钟周期内实现单元内的任何两个元件之间的数据传输的互连。

公开(公告)号：US07750916B2

公开(公告)日：2010-07-06

申请号：US10499875

申请日：2002-12-20

申请人： Martin Whitaker

发明人： Martin Whitaker

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F9/3895 ,  G06F9/345

摘要： A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory address engine with the initializing parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.

摘要翻译： 描述了一种生成表示逻辑空间中的连续点的不连续的存储器地址流的方法。 该方法包括：生成描述逻辑空间中的连续点的初始化参数; 使用初始化参数配置内存地址引擎; 根据初始化参数在存储器地址引擎中执行算法以产生多个不连续的存储器地址; 以及将不连续的存储器地址对准到存储器地址流中以输出到数据存储器。 本发明特别适用于存在多个存储器地址引擎的SIMD处理技术。

公开(公告)号：US20120047350A1

公开(公告)日：2012-02-23

申请号：US13318404

申请日：2010-05-04

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F15/80 ,  G06F9/02

CPC分类号： G06F8/45 ,  G06F9/3887 ,  G06F9/3889 ,  G06F15/8015

摘要： A processing apparatus for processing source code comprising a plurality of single line instructions to implement a desired processing function is described. The processing apparatus comprises:i) a string-based non-associative multiple—SIMD (Single Instruction Multiple Data) parallel processor arranged to process a plurality of different instruction streams in parallel, the processor including: a plurality of data processing elements connected sequentially in a string topology and organised to operate in a multiple—SIMD configuration, the data processing elements being arranged to be selectively and independently activated to take part in processing operations, and a plurality of SIMD controllers, each connectable to a group of selected data processing elements of the plurality of data processing elements for processing a specific instruction stream, each group being defined dynamically during run-time by a single line instruction provided in the source code, andii) a compiler for verifying and converting the plurality of the single line instructions into an executable set of commands for the parallel processor, wherein the processing apparatus is arranged to process each single line instruction which specifies an operation and an active group of selected data processing elements for each SIMD controller that is to take part in the operation.

摘要翻译： 描述了一种用于处理源代码的处理装置，该处理装置包括多条单行指令以实现期望的处理功能。 该处理装置包括：i）基于串的非关联多SIMD（单指令多数据）并行处理器，其被并行处理多个不同的指令流，所述处理器包括：多个数据处理单元， 字符串拓扑并被组织以在多SIMD配置中操作，所述数据处理元件被布置为选择性地和独立地激活以参与处理操作;以及多个SIMD控制器，每个SIMD控制器可连接到一组选择的数据处理元件 用于处理特定指令流的多个数据处理元件中，每个组在运行期间通过在源代码中提供的单行指令动态地定义，以及ii）用于验证和转换多条单行指令的编译器 转换成用于并行处理器的可执行命令集，其中处理 装置被设置为处理指定用于参与该操作的每个SIMD控制器的操作的选定数据处理元件的活动组的每个单行指令。

公开(公告)号：US08046514B2

公开(公告)日：2011-10-25

申请号：US10432309

申请日：2001-11-21

申请人： Martin Whitaker

发明人： Martin Whitaker

IPC分类号： G06F13/372 ,  G06F13/00

CPC分类号： G06F13/4226

摘要： A system and method of broadcasting data to multiple targets across a system bus, such as the peripheral component interconnect (PCI) bus, that does not normally support broadcast transfers, in which one target responds to the bus transaction and the remaining targets listen in on the bus transaction to receive data from the system bus. The responding target stalls the bus transaction when any of the listening targets communicate to the responding target that they are temporarily unable to accept the data on the bus.

摘要翻译： 一种系统和方法，用于通过诸如外围部件互连（PCI）总线的系统总线向多个目标广播数据，这些总线通常不支持广播传输，其中一个目标响应于总线事务，其余目标收听 总线事务从系统总线接收数据。 当任何监听目标与响应目标通信时，响应目标会停止总线事务，使其暂时无法接受总线上的数据。

公开(公告)号：US07865662B2

公开(公告)日：2011-01-04

申请号：US10539493

申请日：2003-12-17

申请人： Ian Jalowiecki ,  Martin Whitaker ,  John Lancaster ,  Donald Boughton

发明人： Ian Jalowiecki ,  Martin Whitaker ,  John Lancaster ,  Donald Boughton

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F15/8038

摘要： An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described. The alternation network comprises: a plurality of alternation modules connected in series together, each module comprising: a plurality of cascaded logic gates arranged to propagate a match parity signal via the gates along at least part of a matching result vector, the matching result vector being generated by execution of a matching instruction on the content addressable memory, and the logic gates being configured to change the parity of the match parity signal in accordance with the matching result vector; and a vector output arranged to output a parity level vector of the propagated match parity signal present at the each gate of the plurality of logic gates; a logic network for dividing the matching result vector into an odd match vector and an even match vector representing respectively odd and even numbered elements of the matching result vector, by use of the parity level vector, and means for writing a selected one of the odd and even match vectors to the content addressable memory.

摘要翻译： 描述了用于实现分割和征服算法的内容可寻址存储器的交替网络。 所述交替网络包括：串联连接的多个交替模块，每个模块包括：多个级联逻辑门，布置成沿着匹配结果向量的至少一部分经由所述门传播匹配奇偶校验信号，所述匹配结果向量为 通过在内容可寻址存储器上执行匹配指令而产生，并且逻辑门被配置为根据匹配结果向量改变匹配奇偶校验信号的奇偶校验; 以及矢量输出，被布置为输出存在于所述多个逻辑门的每个门处的所传播的匹配奇偶校验信号的奇偶校验电平矢量; 用于通过使用奇偶校验电平矢量将匹配结果矢量划分为奇数匹配向量和偶数匹配向量，表示分别为奇数和偶数编号的匹配结果向量元素的偶数向量;以及用于写入奇数 甚至将向量匹配到内容可寻址存储器。

公开(公告)号：US20070254035A1

公开(公告)日：2007-11-01

申请号：US10576909

申请日：2004-10-22

申请人： Jianyuan Hao ,  Martin Whitaker ,  Kevin Shakesheff ,  Steven Howdle

发明人： Jianyuan Hao ,  Martin Whitaker ,  Kevin Shakesheff ,  Steven Howdle

IPC分类号： C08J7/12 ,  A61K9/14 ,  B01J3/00 ,  C08J3/205

CPC分类号： C08J9/12 ,  B01J3/008 ,  B29C44/12 ,  C08J9/14 ,  C08J2201/03 ,  C08J2203/06 ,  C08J2203/08 ,  C08J2203/12 ,  C08J2203/14 ,  C08J2203/142

摘要： Process for preparing active polymer extrudate comprising polymer matrix and guest matter, the process comprising contacting a polymer substrate and guest matter with a plasticising fluid under dense phase, sub critical or supercritical plasticising conditions of elevated temperature and/or pressure to plasticise the polymer substrate and incorporate guest matter and extruding polymer substrate incorporating guest matter under dense phase, sub critical or supercritical conditions via an extrusion orifice into a collection zone or a mould with simultaneous or subsequent release of pressure, whereby extrudate is obtained comprising a solid admixture of polymer matrix and guest matter in form conferred by the orifice or the mould; a novel extrudate; composition thereof and apparatus for the preparation thereof, and use thereof in fibre processing techniques, medical applications such as in delivery of drugs and other agents such as imaging and diagnostic agents, tissue engineering, and as medical devices or aids such as delivery devices or aids for drugs, imaging and diagnostic agents, as tissue engineering devices or aids such as sutures, and the like; as an anti-microbial for example having bacteria-static or -cidal activity; as a natural or synthetic barrier capable of immobilising e.g. naturally occurring or artificially introduced poisons or toxins by e.g. absorption, interaction or reaction; in agrochemical or crop protection applications; in the processing of thermally labile fibres for use in dying, textiles, electronics etc below the polymer Tg, Tm or viscosity; in incorporation of dyes and other thermally labile materials into polymers that cannot be formed by traditional processes e.g. melt extrusion and the like; or in incorporation of surfactants into fibres to control polymer properties.

摘要翻译： 制备包含聚合物基质和客体物质的活性聚合物挤出物的方法，该方法包括在高温和/或高压的密相，亚临界或超临界塑化条件下使聚合物基质和客体物质与增塑流体接触，以塑化聚合物基材和 将客体物质和挤出聚合物基材在密相，亚临界或超临界条件下通过挤出孔引入收集区或模具中，同时或随后释放压力，由此得到包含聚合物基质和固体混合物的固体混合物的挤出物 由孔或模具赋予的形式的客体; 新型挤出物 其制备方法及其制备方法及其在纤维加工技术中的应用，医药应用如药物递送和其它试剂如成像和诊断试剂，组织工程，以及作为医疗装置或辅助剂例如递送装置或助剂 用作药物，成像和诊断剂，作为组织工程装置或诸如缝合线等辅助物品; 作为抗微生物剂，例如具有细菌静止或杀生物活性; 作为能够固定的天然或合成屏障。 天然存在或人为引入的毒素或毒素。 吸收，相互作用或反应; 在农业或作物保护应用中; 在聚合物Tg，Tm或粘度以下的用于染色，纺织品，电子等的热不稳定纤维的加工; 将染料和其他热不稳定材料并入聚合物中，所述聚合物不能通过传统方法形成，例如 熔融挤出等; 或将表面活性剂掺入纤维中以控制聚合物性质。

公开(公告)号：US20060184689A1

公开(公告)日：2006-08-17

申请号：US10539493

申请日：2003-12-17

申请人： Ian Jalowiecki ,  Martin Whitaker ,  John Lancaster ,  Donald Broughton

发明人： Ian Jalowiecki ,  Martin Whitaker ,  John Lancaster ,  Donald Broughton

IPC分类号： G06F15/173

CPC分类号： G06F15/8038

摘要： An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described. The alternation network comprises: a plurality of alternation modules connected in series together, each module comprising: a plurality of cascaded logic gates arranged to propagate a match parity signal via the gates along at least part of a matching result vector, the matching result vector being generated by execution of a matching instruction on the content addressable memory, and the logic gates being configured to change the parity of the match parity signal in accordance with the matching result vector; and a vector output arranged to output a parity level vector of the propagated match parity signal present at the each gate of the plurality of logic gates; a logic network for dividing the matching result vector into an odd match vector and an even match vector representing respectively odd and even numbered elements of the matching result vector, by use of the parity level vector, and means for writing a selected one of the odd and even match vectors to the content addressable memory.

摘要翻译： 描述了用于实现分割和征服算法的内容可寻址存储器的交替网络。 所述交替网络包括：串联连接的多个交替模块，每个模块包括：多个级联逻辑门，布置成沿着匹配结果向量的至少一部分经由所述门传播匹配奇偶校验信号，所述匹配结果向量为 通过在内容可寻址存储器上执行匹配指令而产生，并且逻辑门被配置为根据匹配结果向量改变匹配奇偶校验信号的奇偶校验; 以及矢量输出，被布置为输出存在于所述多个逻辑门的每个门处的所传播的匹配奇偶校验信号的奇偶校验电平矢量; 用于通过使用奇偶校验电平矢量将匹配结果矢量划分为奇数匹配向量和偶数匹配向量，表示分别为奇数和偶数编号的匹配结果向量元素的偶数向量;以及用于写入奇数 甚至将向量匹配到内容可寻址存储器。