公开(公告)号：US07174442B2

公开(公告)日：2007-02-06

申请号：US10432203

申请日：2001-11-21

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F12/00

CPC分类号： G06F9/30043 ,  G06F9/345 ,  G06F13/28

摘要： A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address vector from the non-sequential addresses, and using the address vector in a block fetch command to a data store.

摘要翻译： 描述了对诸如SIMD处理器之类的数据并行处理器执行数据提取操作的方法。 该操作具体涉及使用多个非顺序数据地址。 该方法包括从非顺序地址构建线性地址向量，并且使用块获取命令中的地址向量到数据存储。

公开(公告)号：US20130044825A1

公开(公告)日：2013-02-21

申请号：US13695542

申请日：2011-05-04

申请人： Ian Paul Jalowiecki ,  Martin Whitaker

发明人： Ian Paul Jalowiecki ,  Martin Whitaker

IPC分类号： H04N7/24

CPC分类号： H04N19/43 ,  H04N19/109 ,  H04N19/115 ,  H04N19/149 ,  H04N19/176 ,  H04N19/61

摘要： Methods and apparatus for conducting motion searching are provided. A first 2D array includes interconnected multi-directional shift registers for storing and shifting image values corresponding to a search window within a search region. A second 2D array includes registers for storing image values corresponding to a macroblock. A distortion calculation module is arranged to calculate and output a distortion value corresponding to the difference between image values stored in associated registers of the first and second arrays. The distortion value quantifies the correlation between the search window and the macroblock. The shift registers of the first 2D array are controlled to pass image values between adjacent shift registers to translate the position of the search window within the search region. Distortion values outputted after progressive shifts of the first 2D array are tracked to determine an optimal registration position of the macroblock relative to the search region.

摘要翻译： 提供了进行运动搜索的方法和装置。 第一2D阵列包括用于存储和移动与搜索区域内的搜索窗口对应的图像值的互连的多向移位寄存器。 第二2D阵列包括用于存储对应于宏块的图像值的寄存器。 失真计算模块被布置为计算和输出与存储在第一和第二阵列的相关联的寄存器中的图像值之间的差对应的失真值。 失真值量化搜索窗口和宏块之间的相关性。 控制第一2D阵列的移位寄存器以在相邻移位寄存器之间传递图像值，以将搜索窗口的位置翻译成搜索区域。 跟踪第一2D阵列的逐行移位之后输出的失真值，以确定宏块相对于搜索区域的最佳登记位置。

公开(公告)号：US20050084532A1

公开(公告)日：2005-04-21

申请号：US10505441

申请日：2003-03-11

申请人： Steven Howdle ,  Kevin Shakesheff ,  Martin Whitaker ,  Felicity Rosamari Rose

发明人： Steven Howdle ,  Kevin Shakesheff ,  Martin Whitaker ,  Felicity Rosamari Rose

IPC分类号： C12N11/02 ,  A61K6/083 ,  A61K6/087 ,  A61K6/09 ,  A61K6/097 ,  A61K8/64 ,  A61K8/73 ,  A61K8/96 ,  A61K8/97 ,  A61K8/98 ,  A61K9/16 ,  A61K35/12 ,  A61L27/00 ,  A61L27/38 ,  A61L27/56 ,  A61P43/00 ,  C08J3/20 ,  A61K9/14

CPC分类号： A61L27/3804 ,  A61K9/1647 ,  A61L27/3847 ,  A61L27/56

摘要： A process for the preparation of a polymer composite loaded with functioning matter wherein the process comprises contacting a polymer substrate and functioning matter with a plasticising fluid or mixture of plasticising fluids under plasticising conditions to plasticise and/or swell the polymer and incorporate the functioning matter, and releasing the plasticising fluid to obtain the polymer composite, wherein contacting is at a pressure in the range 1 to 1000 bar and a temperature in the range −200 to +500C, selected in manner that at least a proportion of functioning matter does not freeze or refreeze during processing, or if at a temperature at which freezing or refreezing may occur, that either matter is desiccated or a pressure constraint is applied whereby pressure is in a range having a maximum pressure less than 1000 bar throughout contact of functioning matter and plasticising fluid, whereby at least a proportion of functioning matter retains its function in the polymer composite; A polymer composite obtained with the process; A scaffold comprising a polymer composite loaded with functioning matter, optionally additionally comprising biofunctional materials; An apparatus for use in the preparation of the polymer composite or with use of the process; and use of the composite as a support or scaffold for drug delivery, for use in bioremediation, as a biocatalyst or biobarrier for human or animal or plant matter, for use as a structural component, for example comprising the polymer and optional additional synthetic or natural metal, plastic, carbon or glass fibre mesh, scrim, rod or like reinforcing for medical or surgical insertion, for insertion as a solid monolith into bone or tissue, as fillers or cements for wet insertion into bone or teeth or as solid aggregates or monoliths for orthopaedic implants such as pins, or dental implants such as crowns etc.

摘要翻译： 一种用于制备装载有功能物质的聚合物复合物的方法，其中该方法包括在塑化条件下使聚合物基质和功能物质与塑化流体或塑化流体的混合物接触以使聚合物塑化和/或溶胀并结合功能性物质， 并释放塑化流体以获得聚合物复合材料，其中接触处于1至1000巴的压力和-200至+ 500℃范围内的温度，其选择方式为至少一部分功能物质不会冻结 或在加工过程中重新冻结，或者如果在可能发生冷冻或再冻结的温度下，任何一种物质都被干燥或施加压力约束，从而在功能物质和增塑剂的接触过程中，压力在最大压力小于1000巴的范围内 流体，其中功能物质的至少一部分保留其在聚合物组合物中的功能 现场; 用该方法得到的聚合物复合物; 一种支架，其包含负载功能物质的聚合物复合物，任选地另外包含生物功能材料; 用于制备聚合物复合材料或使用该方法的设备; 以及将复合材料用作药物递送的支持物或支架，用于生物修复，作为用于人或动物或植物物质的生物催化剂或生物保护剂，用作结构成分，例如包含聚合物和任选的其它合成或天然 用于医疗或手术插入的金属，塑料，碳或玻璃纤维网，稀松布，棒或类似的增强物作为固体整体作为骨或组织插入，作为用于湿插入骨或牙齿中的填料或水泥，或作为固体聚集体或整料 用于诸如针或诸如牙冠等牙科植入物的矫形植入物

公开(公告)号：US09195467B2

公开(公告)日：2015-11-24

申请号：US12993793

申请日：2009-05-20

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F9/38 ,  G06F15/80

CPC分类号： G06F9/3887 ,  G06F9/3016 ,  G06F9/3889 ,  G06F9/3891 ,  G06F15/8007

摘要： Improvements Relating to Single Instruction Multiple Data (SIMD) Architectures A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks.

摘要翻译： 关于单指令多数据（SIMD）架构的改进描述了并行处理多个不同处理指令流的并行处理器。 处理器包括多个数据处理单元; 以及多个SIMD（单指令多数据）控制器，每个SIMD（单指令多数据）控制器可连接到多个数据处理单元的一组数据处理单元，并且每个SIMD控制器被布置成处理具有主动连接的数据处理单元的子组的单独处理任务 从数据处理单元组中选择。 并行处理器被布置为在接收到的处理指令流的控制下动态地改变每个SIMD控制器主动连接到的数据处理单元的子组的大小，从而允许每个SIMD控制器主动地连接到不同数量的处理单元 不同的处理任务。

公开(公告)号：US20110191567A1

公开(公告)日：2011-08-04

申请号：US12993793

申请日：2009-05-20

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F9/30

CPC分类号： G06F9/3887 ,  G06F9/3016 ,  G06F9/3889 ,  G06F9/3891 ,  G06F15/8007

摘要： Improvements Relating to Single Instruction Multiple Data (SIMD) Architectures A parallel processor for processing a plurality of different processing instruction streams in parallel is described. The processor comprises a plurality of data processing units; and a plurality of SIMD (Single Instruction Multiple Data) controllers, each connectable to a group of data processing units of the plurality of data processing units, and each SIMD controller arranged to handle an individual processing task with a subgroup of actively connected data processing units selected from the group of data processing units. The parallel processor is arranged to vary dynamically the size of the subgroup of data processing units to which each SIMD controller is actively connected under control of received processing instruction streams, thereby permitting each SIMD controller to be actively connected to a different number of processing units for different processing tasks.

摘要翻译： 关于单指令多数据（SIMD）架构的改进描述了并行处理多个不同处理指令流的并行处理器。 处理器包括多个数据处理单元; 以及多个SIMD（单指令多数据）控制器，每个SIMD（单指令多数据）控制器可连接到多个数据处理单元的一组数据处理单元，并且每个SIMD控制器被布置成处理具有主动连接的数据处理单元的子组的单独处理任务 从数据处理单元组中选择。 并行处理器被布置为在接收到的处理指令流的控制下动态地改变每个SIMD控制器主动连接到的数据处理单元的子组的大小，从而允许每个SIMD控制器主动地连接到不同数量的处理单元 不同的处理任务。

公开(公告)号：US20110185151A1

公开(公告)日：2011-07-28

申请号：US12993801

申请日：2009-05-20

申请人： Martin Whitaker ,  John Lancaster

发明人： Martin Whitaker ,  John Lancaster

IPC分类号： G06F15/80 ,  G06F15/76 ,  G06F9/02

CPC分类号： G06F15/8015

摘要： A parallel processor is described which is operated in a SIMD manner. The processor comprises: a plurality of processing elements connected in a string and grouped into a plurality of processing units, wherein each processing unit comprises a plurality of processing elements which each have direct interconnections with all of the other processing elements within the respective processing unit, the interconnections enabling data transfer between any two elements within a unit to be effected in a single clock cycle.

摘要翻译： 描述了以SIMD方式操作的并行处理器。 处理器包括：串联连接并分组成多个处理单元的多个处理元件，其中每个处理单元包括多个处理元件，每个处理元件与相应处理单元内的所有其它处理元件具有直接互连， 能够在单个时钟周期内实现单元内的任何两个元件之间的数据传输的互连。

公开(公告)号：US07750916B2

公开(公告)日：2010-07-06

申请号：US10499875

申请日：2002-12-20

申请人： Martin Whitaker

发明人： Martin Whitaker

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F9/3895 ,  G06F9/345

摘要： A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initializing parameters describing the contiguous points in the logical space; configuring a memory address engine with the initializing parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.

摘要翻译： 描述了一种生成表示逻辑空间中的连续点的不连续的存储器地址流的方法。 该方法包括：生成描述逻辑空间中的连续点的初始化参数; 使用初始化参数配置内存地址引擎; 根据初始化参数在存储器地址引擎中执行算法以产生多个不连续的存储器地址; 以及将不连续的存储器地址对准到存储器地址流中以输出到数据存储器。 本发明特别适用于存在多个存储器地址引擎的SIMD处理技术。

公开(公告)号：US20120047350A1

公开(公告)日：2012-02-23

申请号：US13318404

申请日：2010-05-04

申请人： John Lancaster ,  Martin Whitaker

发明人： John Lancaster ,  Martin Whitaker

IPC分类号： G06F15/80 ,  G06F9/02

CPC分类号： G06F8/45 ,  G06F9/3887 ,  G06F9/3889 ,  G06F15/8015

摘要： A processing apparatus for processing source code comprising a plurality of single line instructions to implement a desired processing function is described. The processing apparatus comprises:i) a string-based non-associative multiple—SIMD (Single Instruction Multiple Data) parallel processor arranged to process a plurality of different instruction streams in parallel, the processor including: a plurality of data processing elements connected sequentially in a string topology and organised to operate in a multiple—SIMD configuration, the data processing elements being arranged to be selectively and independently activated to take part in processing operations, and a plurality of SIMD controllers, each connectable to a group of selected data processing elements of the plurality of data processing elements for processing a specific instruction stream, each group being defined dynamically during run-time by a single line instruction provided in the source code, andii) a compiler for verifying and converting the plurality of the single line instructions into an executable set of commands for the parallel processor, wherein the processing apparatus is arranged to process each single line instruction which specifies an operation and an active group of selected data processing elements for each SIMD controller that is to take part in the operation.

摘要翻译： 描述了一种用于处理源代码的处理装置，该处理装置包括多条单行指令以实现期望的处理功能。 该处理装置包括：i）基于串的非关联多SIMD（单指令多数据）并行处理器，其被并行处理多个不同的指令流，所述处理器包括：多个数据处理单元， 字符串拓扑并被组织以在多SIMD配置中操作，所述数据处理元件被布置为选择性地和独立地激活以参与处理操作;以及多个SIMD控制器，每个SIMD控制器可连接到一组选择的数据处理元件 用于处理特定指令流的多个数据处理元件中，每个组在运行期间通过在源代码中提供的单行指令动态地定义，以及ii）用于验证和转换多条单行指令的编译器 转换成用于并行处理器的可执行命令集，其中处理 装置被设置为处理指定用于参与该操作的每个SIMD控制器的操作的选定数据处理元件的活动组的每个单行指令。

公开(公告)号：US08046514B2

公开(公告)日：2011-10-25

申请号：US10432309

申请日：2001-11-21

申请人： Martin Whitaker

发明人： Martin Whitaker

IPC分类号： G06F13/372 ,  G06F13/00

CPC分类号： G06F13/4226

摘要： A system and method of broadcasting data to multiple targets across a system bus, such as the peripheral component interconnect (PCI) bus, that does not normally support broadcast transfers, in which one target responds to the bus transaction and the remaining targets listen in on the bus transaction to receive data from the system bus. The responding target stalls the bus transaction when any of the listening targets communicate to the responding target that they are temporarily unable to accept the data on the bus.

摘要翻译： 一种系统和方法，用于通过诸如外围部件互连（PCI）总线的系统总线向多个目标广播数据，这些总线通常不支持广播传输，其中一个目标响应于总线事务，其余目标收听 总线事务从系统总线接收数据。 当任何监听目标与响应目标通信时，响应目标会停止总线事务，使其暂时无法接受总线上的数据。

公开(公告)号：US07865662B2

公开(公告)日：2011-01-04

申请号：US10539493

申请日：2003-12-17

申请人： Ian Jalowiecki ,  Martin Whitaker ,  John Lancaster ,  Donald Boughton

发明人： Ian Jalowiecki ,  Martin Whitaker ,  John Lancaster ,  Donald Boughton

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F15/8038

摘要： An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described. The alternation network comprises: a plurality of alternation modules connected in series together, each module comprising: a plurality of cascaded logic gates arranged to propagate a match parity signal via the gates along at least part of a matching result vector, the matching result vector being generated by execution of a matching instruction on the content addressable memory, and the logic gates being configured to change the parity of the match parity signal in accordance with the matching result vector; and a vector output arranged to output a parity level vector of the propagated match parity signal present at the each gate of the plurality of logic gates; a logic network for dividing the matching result vector into an odd match vector and an even match vector representing respectively odd and even numbered elements of the matching result vector, by use of the parity level vector, and means for writing a selected one of the odd and even match vectors to the content addressable memory.

摘要翻译： 描述了用于实现分割和征服算法的内容可寻址存储器的交替网络。 所述交替网络包括：串联连接的多个交替模块，每个模块包括：多个级联逻辑门，布置成沿着匹配结果向量的至少一部分经由所述门传播匹配奇偶校验信号，所述匹配结果向量为 通过在内容可寻址存储器上执行匹配指令而产生，并且逻辑门被配置为根据匹配结果向量改变匹配奇偶校验信号的奇偶校验; 以及矢量输出，被布置为输出存在于所述多个逻辑门的每个门处的所传播的匹配奇偶校验信号的奇偶校验电平矢量; 用于通过使用奇偶校验电平矢量将匹配结果矢量划分为奇数匹配向量和偶数匹配向量，表示分别为奇数和偶数编号的匹配结果向量元素的偶数向量;以及用于写入奇数 甚至将向量匹配到内容可寻址存储器。