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    Neural processing unit capable of reusing data and method thereof
    1.
    发明授权
    Neural processing unit capable of reusing data and method thereof 有权

    公开(公告)号：US12118453B2

    公开(公告)日：2024-10-15

    申请号：US18083379

    申请日：2022-12-16

    申请人： DEEPX CO., LTD.

    发明人： JungBoo Park ,  Hansuk Yoo

    IPC分类号： G06N3/06 ,  G06N3/063

    CPC分类号： G06N3/063

    摘要： A neural processing unit includes a mode selector configured to select a first mode or a second mode; and processing element (PE) array operating in one of the first mode and the second mode and including a plurality of processing elements arranged in PE rows and PE columns, the PE array configured to receive an input of first input data and an input of second input data, respectively. In the second mode, the first input data is inputted in a PE column direction of the PE array and is transmitted along the PE column direction while being delayed by a specific number of clock cycles, and the second input data is broadcast to the plurality of processing elements of the PE array to which the first input data is delayed by the specific number of clock cycles.

    METHOD FOR PERFORMING AGING TEST ON SEMICONDUCTOR USED FOR NEURAL NETWORK
    3.
    发明公开
    METHOD FOR PERFORMING AGING TEST ON SEMICONDUCTOR USED FOR NEURAL NETWORK 审中-公开

    公开(公告)号：US20240274225A1

    公开(公告)日：2024-08-15

    申请号：US18648655

    申请日：2024-04-29

    申请人： DEEPX CO., LTD.

    发明人： Lok Won KIM

    IPC分类号： G11C29/00 ,  G05B19/418 ,  G06F11/26 ,  G11C29/10

    CPC分类号： G11C29/78 ,  G05B19/41875 ,  G06F11/26 ,  G11C29/10 ,  G05B2219/32368 ,  G05B2219/45031

    摘要： Provided is a method for performing an aging test on a neural processing unit (NPU) with a capability of a runtime test. The method may comprise: performing an aging test on the NPU which comprises a plurality of functional components. The plurality of functional components may comprise at least one memory and plural processing elements. The performing of the aging test may include: performing a scan test on the NPU to verify whether at least one functional component in the NPU is defective or not; and performing a memory test on the at least one memory. At least one of the scan test and the memory test may be repeatedly performed to put a stress on the NPU for the aging test. The aging test may be repeated by a predetermined number.

    IMAGE PROCESSING METHOD USING ARTIFICIAL NEURAL NETWORK, AND NEURAL PROCESSING UNIT
    6.
    发明公开
    IMAGE PROCESSING METHOD USING ARTIFICIAL NEURAL NETWORK, AND NEURAL PROCESSING UNIT 审中-公开

    公开(公告)号：US20240104912A1

    公开(公告)日：2024-03-28

    申请号：US18267095

    申请日：2022-07-01

    申请人： DEEPX CO., LTD.

    发明人： Lok Won KIM ,  Shin Woo JEON

    IPC分类号： G06V10/82 ,  G06V10/70

    CPC分类号： G06V10/82 ,  G06V10/87

    摘要： An image processing method includes receiving an image including an object; classifying at least one object in the image using a first model on the basis of an artificial neural network configured to classify the at least one object by inputting the image; and obtaining an image having improved quality according to the at least one object by inputting the image in which the at least one object is classified by using at least one model among a plurality of second models on the basis of an artificial neural network configured to output a specialized processing applied image according to a particular object by inputting the received image.

    SOC FOR OPERATING PLURAL NPUS ACCORDING TO PLURAL CLOCK SIGNALS HAVING MULTI-PHASES
    7.
    发明公开
    SOC FOR OPERATING PLURAL NPUS ACCORDING TO PLURAL CLOCK SIGNALS HAVING MULTI-PHASES 审中-公开

    公开(公告)号：US20240012445A1

    公开(公告)日：2024-01-11

    申请号：US18473746

    申请日：2023-09-25

    申请人： DEEPX CO., LTD.

    发明人： Lok Won KIM ,  Jin Gun SONG ,  Seong Jin LEE

    IPC分类号： G06F1/08 ,  G06F15/80

    CPC分类号： G06F1/08 ,  G06F15/80

    摘要： A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

    NEURAL PROCESSING UNIT CAPABLE OF SWITCHING ANN MODELS
    8.
    发明公开
    NEURAL PROCESSING UNIT CAPABLE OF SWITCHING ANN MODELS 审中-公开

    公开(公告)号：US20230316040A1

    公开(公告)日：2023-10-05

    申请号：US18312660

    申请日：2023-05-05

    申请人： DEEPX CO., LTD.

    发明人： You Jun KIM ,  Ha Joon YU ,  Lok Won KIM

    IPC分类号： G06N3/04

    CPC分类号： G06N3/04

    摘要： A neural processing unit (NPU) mounted on a movable device for detecting object is provided. The NPU may comprise a plurality of processing elements (PEs), configured to process an operation of a first artificial neural network model (ANN) and an operation of a second ANN different from the first ANN; a memory configured to store a portion of a data of the first ANN and the second ANN; and a controller configured to control the PEs and the memory to selectively perform a convolution operation of the first ANN or the second ANN based on a determination data, wherein the determination data may include an object detection performance data of the first ANN and the second ANN, respectively.

    Video-stream format for machine analysis using NPU
    9.
    发明授权
    Video-stream format for machine analysis using NPU 有权

    公开(公告)号：US11743477B1

    公开(公告)日：2023-08-29

    申请号：US17897487

    申请日：2022-08-29

    申请人： DEEPX CO., LTD.

    发明人： IlMyeong Im ,  SunMi Lee

    IPC分类号： H04N19/42 ,  H04N19/30 ,  H04N19/172 ,  G06N3/063

    CPC分类号： H04N19/42 ,  G06N3/063 ,  H04N19/172 ,  H04N19/30

    摘要： A neural processing unit (NPU) for decoding video and/or feature map may include at least one processing element (PE) for an artificial neural network (ANN), the at least one PE to receive and decode a bitstream. The bitstream is received in units of frames, and one frame includes a weight for an ANN model, data of a base layer, and data of a plurality of enhancement layers. An NPU for encoding video and/or feature map may include at least one processing element (PE) for an artificial neural network (ANN), the at least one PE to encode an input video or feature map and to transmit the encoded input video or feature map as a bitstream. The at least one PE transmits the bitstream in units of frames, and one frame includes a weight for an ANN model, data of a base layer, and data of a plurality of enhancement layers.

    SYSTEM-ON-CHIP AND METHOD FOR PERFORMING DIAGNOSE DURING RUNTIME
    10.
    发明公开
    SYSTEM-ON-CHIP AND METHOD FOR PERFORMING DIAGNOSE DURING RUNTIME 审中-公开

    公开(公告)号：US20230244583A1

    公开(公告)日：2023-08-03

    申请号：US18299185

    申请日：2023-04-12

    申请人： DEEPX CO., LTD.

    发明人： Lok Won KIM

    IPC分类号： G06F11/273 ,  G06N3/02

    CPC分类号： G06F11/273 ,  G06N3/02 ,  G06F2213/0038

    摘要： A system on chip (SoC) for testing a component in a system during runtime includes a plurality of functional components; a system bus for allowing the plurality of functional components to communicate with each other; one or more wrappers, each connected to one of the plurality of functional components; and an in-system component tester (ICT). The ICT monitors, via the wrappers, states of the functional components; selects, as a component under test (CUT), at least one functional component in an idle state; tests, via the wrappers, the selected at least one functional component; interrupts the testing step with respect to the selected at least one functional component, based on a detection of a collision with an access from the system bus to the selected at least one functional component; and allows a connection of the at least one functional component to the system bus, based on the interrupting step.