公开(公告)号：US08319563B2

公开(公告)日：2012-11-27

申请号：US13044112

申请日：2011-03-09

申请人： Iain Ross Mactaggart

发明人： Iain Ross Mactaggart

IPC分类号： H03L7/08 ,  H03K5/13

CPC分类号： G06F1/022 ,  H03L7/0994 ,  H03L7/16

摘要： Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

摘要翻译： 实现具有减少的模拟组件的数字控制振荡器的装置和电路的实施例。 在一个示例中，数字控制振荡器可以包括由失速电路控制的相位累加器，以选择性地停止相位累加器。 在一些示例中，数控振荡器可以包括基于相位累加器的输出来选择相位选择电路的多个相位的相位选择电路。 在一些示例中，这些选择的相位然后可以由相位内插器使用以产生合成时钟信号。

公开(公告)号：US08890595B2

公开(公告)日：2014-11-18

申请号：US13895849

申请日：2013-05-16

申请人： Fmax Technologies, Inc.

发明人： Iain Ross Mactaggart

IPC分类号： H03K3/00 ,  H03H11/16 ,  H03K5/13 ,  H03L7/16

CPC分类号： H03L7/16 ,  G06F1/025 ,  H03K5/13

摘要： Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

摘要翻译： 实现具有减少的模拟组件的数字控制振荡器的装置和电路的实施例。 在一个示例中，数字控制振荡器可以包括由失速电路控制的相位累加器，以选择性地停止相位累加器。 在一些示例中，数控振荡器可以包括基于相位累加器的输出来选择相位选择电路的多个相位的相位选择电路。 在一些示例中，这些选择的相位然后可以由相位内插器使用以产生合成时钟信号。

公开(公告)号：US10084623B1

公开(公告)日：2018-09-25

申请号：US14946397

申请日：2015-11-19

申请人： Fmax Technologies, Inc.

发明人： Iain Ross Mactaggart ,  David Erich Tetzlaff

IPC分类号： H04L25/03 ,  H04L27/01 ,  H04L7/00

CPC分类号： H04L7/0033 ,  H04L7/0004 ,  H04L7/0079 ,  H04L7/033 ,  H04L25/03019 ,  H04L27/01

摘要： Apparatus and methods are provide for a multichannel clock and data recovery (CDR) device that shares information between channels. In an example, a multiple channel communication circuit can include a plurality of clock and data recovery (CDR) circuits, each CDR circuit of the plurality of CDR circuits associated with a channel of the multiple channel communication circuit. In certain examples, each CDR circuit can be configured to detect an incoming stream of data from the channel, to determine a setting of one or more parameters for correctly sampling the data from the incoming stream, and to share an indication of the setting of the one or more parameters to an adjacent CDR circuit of the plurality of CDR circuits.

公开(公告)号：US09966994B2

公开(公告)日：2018-05-08

申请号：US15098031

申请日：2016-04-13

申请人： Fmax Technologies, Inc.

发明人： David Erich Tetzlaff ,  Iain Ross Mactaggart

IPC分类号： H04L1/00 ,  H04B3/462 ,  H04L12/26 ,  H04L7/033 ,  H04L7/10

CPC分类号： H04B3/462 ,  H04L1/00 ,  H04L7/0338 ,  H04L7/10 ,  H04L43/022

摘要： Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.