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公开(公告)号：US20240348165A1
公开(公告)日：2024-10-17
申请号：US18627816
申请日：2024-04-05
发明人： Zhiyuan Shen , Peng Zhou , Zhaolong Yu , Zhengyong Ding
CPC分类号： H02M3/1566 , H02M1/0019 , H02M1/0038 , H02M3/1584
摘要： A method of controlling a power converter comprising N phase power stage circuits coupled in parallel, where N is a positive integer, can include: controlling an operating mode of the power converter; and disabling at least one pulse in a first trigger signal for controlling each phase power stage circuit in the power converter to start operating, in order to reduce a fluctuation amplitude of the output signal.
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公开(公告)号：US11652407B2
公开(公告)日：2023-05-16
申请号：US17522106
申请日：2021-11-09
发明人： Lang Mao
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： A driving circuit for a switching capacitor converter, the driving circuit including: a first driver, a second driver, a third driver, and a fourth driver, configured to respectively drive a first power switch, a second power switch, a third power switch, and a fourth power switch according to corresponding logic control signals; and a charge pump circuit configured to raise a DC bus voltage by a first voltage to obtain a pumping voltage to supply power to the first driver, where the first, second, third, and fourth power switches are sequentially coupled in series between the DC bus voltage and a reference ground.
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公开(公告)号：US20230102822A1
公开(公告)日：2023-03-30
申请号：US17941716
申请日：2022-09-09
发明人： Zhen Zhang , Wang Zhang , Junyan Sun
摘要： A power conversion module can include: an i-th level structure comprising 2i-1 basic units, a second terminal of each basic unit in each level structure respectively connected to first terminals of two basic units in a next level structure, where a first terminal of a first basic unit in a first-level structure is used as a first terminal of the power conversion module; an N-th level structure comprising 2N-1 balance units, where second terminals of each balance unit are connected as a second terminal of the power conversion module, and second terminals of each basic unit in an (N−1)th level structure are respectively connected to first terminals of two balance units in the N-th level structure; and where each basic unit comprises a switched capacitor circuit, N is a positive integer greater than or equal to 2, i is a positive integer, and 1≤i≤N−1.
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公开(公告)号：US20220376814A1
公开(公告)日：2022-11-24
申请号：US17735614
申请日：2022-05-03
发明人： Zhongjie Sun , Cheng Liang
IPC分类号： H04L1/00 , H04W28/02 , H04L65/1066 , H04W4/80
摘要： A data forwarding method and apparatus in a Bluetooth Mesh network are disclosed. According to the present disclosure, on the basis of not changing the original Bluetooth protocol, switching is performed to transmit the forwarded data at different transmission rates multiple times. The transmission distance difference between different transmission rates is used to achieve regional flood forwarding, thereby reducing a large number of flooding of device nodes in the network and avoiding network congestion, and improving the performance of the entire Bluetooth Mesh network.
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公开(公告)号：US20220324272A1
公开(公告)日：2022-10-13
申请号：US17699549
申请日：2022-03-21
发明人： Jiajie Fu , Chunbo Lin
摘要： A tire localization method for a vehicle, can include: matching a first Bluetooth module in each tire of the vehicle with a second Bluetooth module of a Bluetooth host in the vehicle; acquiring first data representing a received signal strength indication of a first radio frequency signal sent by the first Bluetooth module in each tire; acquiring an angle of arrival of the first Bluetooth module in each tire relative to the second Bluetooth module; and locating each tire based on the first data and the angle of arrival.
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公开(公告)号：US20220181968A1
公开(公告)日：2022-06-09
申请号：US17522106
申请日：2021-11-09
发明人： Lang Mao
IPC分类号： H02M3/07
摘要： A driving circuit for a switching capacitor converter, the driving circuit including: a first driver, a second driver, a third driver, and a fourth driver, configured to respectively drive a first power switch, a second power switch, a third power switch, and a fourth power switch according to corresponding logic control signals; and a charge pump circuit configured to raise a DC bus voltage by a first voltage to obtain a pumping voltage to supply power to the first driver, where the first, second, third, and fourth power switches are sequentially coupled in series between the DC bus voltage and a reference ground.
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公开(公告)号：US20210173994A1
公开(公告)日：2021-06-10
申请号：US17139323
申请日：2020-12-31
发明人： Kaipeng LIN , Yanrong Li , Geng Bai
IPC分类号： G06F30/343 , G06F30/3312
摘要： The present invention discloses a method and system for viewing simulation signals of a digital product. When a controller controls a FPGA to perform a first simulation verification, the controller reads and records status data of all external ports of the digital product in real time, and reads and records all internal status data of the digital product once at each interval. After the FPGA simulation is completed, if data of a certain clock cycle of the digital product needs to be viewed in a backtracking manner, the controller loads the digital product into the software simulator to perform a second simulation verification, and sets the external port status data and the internal status data recorded at said last time point as an initial status of the digital product. By adopting the technical solution, all simulated data of any clock cycle can be viewed quickly in a backtracking manner.
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公开(公告)号：US20210173989A1
公开(公告)日：2021-06-10
申请号：US17139294
申请日：2020-12-31
发明人： Kaipeng LIN , Yanrong LI , Yucheng WANG
IPC分类号： G06F30/331
摘要： The present invention discloses a simulation signal viewing method and system for a digital product. Firstly, a controller controls a FPGA to perform a first simulation verification by reading and recording status data of all external ports of the digital product in real time, and reading and recording all internal status data of the digital product once at each interval. After the simulation is completed, if data of a certain clock cycle of the digital product needs to be viewed in a backtracking manner, the controller reads the internal status data of the digital product stored at a last time point before the certain clock cycle and the status data of the external ports at the last time point, and, using the read data as initial operating status data for a second simulation verification, starts the FPGA to operate to one clock cycle before the certain clock cycle.
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9.发明授权公开(公告)号：US09628265B2
公开(公告)日：2017-04-18
申请号：US14758105
申请日：2014-06-18
发明人： Liangqing Wang , Dawu Gu , Zheng Guo , Junrong Liu , Feng Deng
CPC分类号： H04L9/003 , G09C1/00 , H04L9/0618 , H04L2209/046
摘要： The invention discloses an encryption processing device and a method capable of defending differential power analysis attack. In the encryption processing device provided by an embodiment of the invention, a SecMasking unit is achieved in a structure that a universal random masking technique services as a basis; a SecPrepare unit is achieved in a structure that a bitwise XOR device services as a basis; and a SecSbox unit is achieved in a mode that table look-up results are updated longitudinally and transversely in real time on the basis of a random masking technique. According to the encryption processing device and method, work power consumption of a cryptographic operation equipment circuit can have no relation with operation data and calculation operations. In addition, the encryption processing device and method can be widely used for encrypting and decrypting operation cryptographic equipment needing high safety performance.
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公开(公告)号：US20240333149A1
公开(公告)日：2024-10-03
申请号：US18617915
申请日：2024-03-27
发明人： Siyuan Chen , Sihua Wen , Yu Wu
CPC分类号： H02M3/07 , H02M1/0095 , H02M1/32 , H02M3/158
摘要： A multi-level converter can include: a switch capacitor circuit having M flying capacitors and 2*(M+1) transistors, where M is a positive integer; an inductive element; a balance circuit coupled to a common node of the switch capacitor circuit and the inductive element; and where the balance sub-circuit includes at least one balance sub-circuit, a balance switch, and a balance capacitor, and where the flying capacitor and the balance capacitor are coupled to each other in one of series and parallel connections by controlling the balance switch to selectively to be turned on and off.
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