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1.发明授权Advanced processor messaging apparatus including fast messaging ring components configured to accomodate point-to-point transfer of non-memory related messages 失效高级处理器消息传递装置包括被配置为容纳非存储器相关消息的点对点传送的快速消息传送环组件公开(公告)号：US07627717B2
公开(公告)日：2009-12-01
申请号：US11961884
申请日：2007-12-20
申请人： David T. Hass , Abbas Rashid
发明人： David T. Hass , Abbas Rashid
CPC分类号： H04L45/52 , G06F12/0813 , G06F2212/154 , G06F2212/62 , H04L12/42 , H04L49/00 , H04L49/15 , H04L49/30 , H04L49/35
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。
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公开(公告)号：US07536631B1
公开(公告)日：2009-05-19
申请号：US10452229
申请日：2003-06-03
CPC分类号： H03M13/13 , H03M13/3761 , H04L1/004 , H04L1/22
摘要： A communication circuit for verified communication comprising a transmitter having input terminals to receive a data word, an encoder configured to encode the data word to create an encoded word different from the data word, and output terminals configured to transmit the data word and the encoded word. A receiver is coupled to the transmitter and includes input terminals to receive the data word as a received word and the encoded word, a decoder configured to decode the encoded word to create a decoded word, and a comparator configured to compare the received word and the decoded word to create a select signal, and a selector responsive to the select signal and configured to select the received data word or the decoded word based at least in part on the select signal. Advantages of the invention include the ability to verify redundant received data without decreasing bandwidth or increasing latency.
摘要翻译： 一种用于验证通信的通信电路，包括具有用于接收数据字的输入端的发送器，被配置为对数据字进行编码以创建与数据字不同的编码字的编码器，以及被配置为发送数据字和编码字的输出端 。 接收机耦合到发射机，并且包括用于接收数据字作为接收字和编码字的输入端，被配置为解码编码字以产生解码字的解码器，以及比较器，被配置为将接收到的字与 解码字以产生选择信号，以及选择器，其响应于所述选择信号，并且被配置为至少部分地基于所述选择信号来选择所接收的数据字或所述解码字。 本发明的优点包括在不减少带宽或增加延迟的情况下验证冗余接收数据的能力。
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公开(公告)号：US07487369B1
公开(公告)日：2009-02-03
申请号：US09562071
申请日：2000-05-01
申请人： Mayank Gupta , Edward T. Pak , Javier Villagomez , Peter H. Voss
发明人： Mayank Gupta , Edward T. Pak , Javier Villagomez , Peter H. Voss
CPC分类号： G06F1/3203 , G06F1/3275 , G06F12/0802 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： The invention provides a cache architecture that selectively powered-up a portion of data array in a pipelined cache architecture. A tag array is first powered-up, but the data array is not powered-up during this time, to determine whether there is a tag hit from the decoded index address comparing to the tag compare data. If there is a tag hit, during a later time, a data array is then powered-up at that time to enable a cache line which corresponds with the tag hit for placing onto a data bus. The power consumed by the tag represents a fraction of the power consumed by the data array. A significant power is conserved during the time in which the tag array is assessing whether a tag hit occurs while the data array is not powered-on at this point.
摘要翻译： 本发明提供一种高速缓存架构，其选择性地加电流水线高速缓存结构中的数据阵列的一部分。 标签阵列首先被加电，但在此期间数据阵列未上电，以确定与标签比较数据相比，是否存在来自解码的索引地址的标签命中。 如果有一个标签命中，在稍后的时间内，数据阵列然后被加电，以启用与标签命中对应的高速缓存行放置在数据总线上。 标签消耗的功率代表数据阵列消耗的功率的一小部分。 在标签阵列评估在此时数据阵列未通电的情况下是否发生标签命中的时间内，节省了大量功率。
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4.发明授权Method and apparatus for providing internal table extensibility based on product configuration 失效基于产品配置提供内部表可扩展性的方法和装置公开(公告)号：US07471682B2
公开(公告)日：2008-12-30
申请号：US10687789
申请日：2003-10-17
IPC分类号： H04L12/56
CPC分类号： H04L41/0816
摘要： A configurable lookup table system including a first controller coupled to a first lookup table and a second controller coupled to a second lookup table is disclosed. The first controller configures the first lookup table for a first type lookup, which can be a Layer 2 or Media Access Control (MAC) type. The second controller configures the second lookup table based on a mode determination. If in a first mode, the second lookup table can be configured for a second type lookup, which can be a Layer 3 or Internet Protocol (IP) type. If in a second mode, the second lookup table can be configured for the first type lookup. This approach provides an efficient scheme for controlling and using multiple internal lookup tables for a variety of product configurations.
摘要翻译： 公开了一种可配置的查找表系统，其包括耦合到第一查找表的第一控制器和耦合到第二查找表的第二控制器。 第一个控制器为第一个类型查找配置第一个查找表，它可以是第二层或介质访问控制（MAC）类型。 第二控制器基于模式确定来配置第二查找表。 如果在第一模式中，可以将第二查找表配置为第二类型查找，其可以是第3层或互联网协议（IP）类型。 如果在第二模式中，可以为第一类型查找配置第二查找表。 这种方法提供了一种用于控制和使用多种内部查找表用于各种产品配置的有效方案。
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5.发明授权Advanced processor with implementation of memory ordering on a ring based data movement network 失效在基于环的数据移动网络上实现存储器排序的高级处理器公开(公告)号：US07461215B2
公开(公告)日：2008-12-02
申请号：US10930187
申请日：2004-08-31
申请人： David T. Hass
发明人： David T. Hass
CPC分类号： H04L47/624 , H04L47/24 , H04L47/50 , H04L47/568 , H04L49/90 , H04L49/9094
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。
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公开(公告)号：US07538696B2
公开(公告)日：2009-05-26
申请号：US11849166
申请日：2007-08-31
IPC分类号： H03M7/34
CPC分类号： H03M7/40 , H03M7/3086
摘要： An apparatus to implement Huffman decoding in an INFLATE process in a compression engine. An embodiment of the apparatus includes a bit buffer, a set of comparators, and a lookup table. The bit buffer stores a portion of a compressed data stream. The set of comparators compares the portion of the compressed data stream with a plurality of predetermined values. The lookup table stores a plurality of LZ77 code segments and outputs one of the LZ77 code segments corresponding to an index at least partially derived from a comparison result from the set of comparators.
摘要翻译： 一种用于在压缩引擎中的INFLATE过程中实现霍夫曼解码的装置。 该装置的实施例包括位缓冲器，一组比较器和查找表。 比特缓冲器存储压缩数据流的一部分。 比较器组将压缩数据流的部分与多个预定值进行比较。 查找表存储多个LZ77代码段，并且输出与至少部分地从比较器组的比较结果导出的索引相对应的LZ77代码段中的一个。
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公开(公告)号：US07538695B2
公开(公告)日：2009-05-26
申请号：US11824501
申请日：2007-06-29
申请人： Robert William Laker , David T Hass
发明人： Robert William Laker , David T Hass
IPC分类号： H03M7/34
CPC分类号： H03M7/3086
摘要： An apparatus to implement a deflate process in a compression engine. An embodiment of the apparatus includes a hash table, a dictionary, comparison logic, and encoding logic. The hash table is configured to hash a plurality of characters of an input data stream to provide a hash address. The dictionary is configured to provide a plurality of distance values in parallel based on the hash address. The distance values are stored in the dictionary. The comparison logic is configured to identify a corresponding length for each matching distance value from the plurality of distance values. The encoding logic is configured to encode the longest length and the matching distance value as a portion of a LZ77 code stream.
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8.发明授权Advanced processor with use of bridges on a data movement ring for optimal redirection of memory and I/O traffic 失效高级处理器在数据移动环上使用桥接器，以最佳地重定向内存和I / O流量公开(公告)号：US07509462B2
公开(公告)日：2009-03-24
申请号：US10930179
申请日：2004-08-31
申请人： David T. Hass , Ricardo Ramirez
发明人： David T. Hass , Ricardo Ramirez
CPC分类号： H04L45/52 , G06F12/0813 , G06F2212/154 , G06F2212/62 , H04L12/42 , H04L49/00 , H04L49/15 , H04L49/30 , H04L49/35
摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。
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9.发明授权公开(公告)号：US07447204B2
公开(公告)日：2008-11-04
申请号：US10766695
申请日：2004-01-27
申请人： Paolo Narvaez
发明人： Paolo Narvaez
IPC分类号： H04L12/56
CPC分类号： H04L47/2441 , H04L47/10 , H04L47/2408 , H04L47/31
摘要： A system and method for classification of data units in a network device acts as a bridge in heterogeneous networks, provides many different services and provisions many different transport mechanisms. The data classifier generates an ID that is internally used by the network device in managing, queuing, processing, scheduling and routing to egress the data unit. This internal ID enables the device to accept any type of data units from any physical/logical ports or channels and output those data units on any physical/logical ports or channels that are available. The device utilizes learning on a per-flow basis and can enable the device to identify and process data units used in private line services and private LAN services.
摘要翻译： 用于网络设备中数据单元分类的系统和方法在异构网络中充当桥梁，提供许多不同的服务，并提供许多不同的传输机制。 数据分类器生成内部由网络设备用于管理，排队，处理，调度和路由以出口数据单元的ID。 该内部ID使设备能够从任何物理/逻辑端口或通道接收任何类型的数据单元，并在可用的任何物理/逻辑端口或通道上输出这些数据单元。 该设备利用基于每流的学习，并且可以使设备识别和处理在专线服务和专用LAN服务中使用的数据单元。
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公开(公告)号：US07426216B2
公开(公告)日：2008-09-16
申请号：US10302015
申请日：2002-11-21
IPC分类号： H04L12/54
CPC分类号： H04L49/25 , H04L49/101 , H04L49/3027 , H04L49/3045
摘要： The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. It also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. An output terminal is configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. The Arbiter is configured to scan the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs.
摘要翻译： 本发明涉及一种交叉开关控制器，其包括输入端子，该输入端子被配置为从包括一组分组的一组虚拟输出队列接收一组服务请求信号。 它还包括耦合到输入端并被配置为以矩阵的形式表示服务请求信号集合的矩阵电路，其中每个服务请求信号由行位置M和列位置N描述。输出端是 被配置为在历元期间接收该组分组的一部分，仲裁器电路被配置为在该时期期间迭代地扫描该矩阵，并向该虚拟输出队列发出一组授权信号以确定哪个服务请求被授予，以及一个仲裁器控制器 被配置为以不冲突的矩阵元素的阵列启动仲裁器电路。 仲裁器被配置为在第一纪元期间扫描矩阵，发出授权信号集合，允许一组授权的服务请求基本上完成，并且如果需要，在随后的时期期间扫描矩阵。
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